| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | Require latest Verific build | Miodrag Milanovic | 2021-01-30 | 1 | -1/+1 | |
| | | | | | ||||||
| * | | | | ast: fix dump_vlog display of casex/casez | Marcelina Kościelnicka | 2021-01-29 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | The first child of AST_CASE is the case expression, it's subsequent childrean that are AST_COND* and can be used to discriminate the type of the case. | |||||
| * | | | | verilog: strip leading and trailing spaces in macro args | Zachary Snow | 2021-01-28 | 1 | -1/+5 | |
| |/ / / | ||||||
| * | | | Merge pull request #2550 from zachjs/macro-arg-spaces | whitequark | 2021-01-25 | 1 | -1/+0 | |
| |\ \ \ | | | | | | | | | verilog: allow spaces in macro arguments | |||||
| | * | | | verilog: allow spaces in macro arguments | Zachary Snow | 2021-01-20 | 1 | -1/+0 | |
| | | | | | ||||||
| * | | | | dpi: Support for chandle type | David Shah | 2021-01-23 | 1 | -1/+16 | |
| | |/ / |/| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | Allow combination of rand and const modifiers | Zachary Snow | 2021-01-21 | 1 | -2/+10 | |
| | | | | ||||||
| * | | | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ ↵ | Claire Xenia Wolf | 2021-01-20 | 1 | -18/+18 | |
| | | | | | | | | | | | | | | | | | | | flavored Verific Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | | | sv: fix support wire and var data type modifiers | Zachary Snow | 2021-01-20 | 1 | -9/+23 | |
| |/ / | ||||||
| * | | Fix input/output attributes when resolving typedef of wire | Kamil Rakoczy | 2021-01-18 | 1 | -0/+3 | |
| | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| * | | Parse package user type in module port list | Lukasz Dalek | 2021-01-18 | 1 | -30/+32 | |
| |/ | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| * | Merge pull request #2518 from zachjs/recursion | whitequark | 2021-01-01 | 2 | -8/+28 | |
| |\ | | | | | verilog: improved support for recursive functions | |||||
| | * | verilog: improved support for recursive functions | Zachary Snow | 2020-12-31 | 2 | -8/+28 | |
| | | | ||||||
| * | | sv: complete support for implied task/function port directions | Zachary Snow | 2020-12-31 | 1 | -0/+10 | |
| |/ | ||||||
| * | Fix elaboration of whole memory words used as indices | Zachary Snow | 2020-12-26 | 1 | -1/+8 | |
| | | ||||||
| * | Fix constants bound to redeclared function args | Zachary Snow | 2020-12-26 | 1 | -5/+16 | |
| | | | | | | | | | The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`. | |||||
| * | Merge pull request #2501 from zachjs/genrtlil-tern-sign | whitequark | 2020-12-23 | 1 | -0/+1 | |
| |\ | | | | | genrtlil: fix mux2rtlil generated wire signedness | |||||
| | * | genrtlil: fix mux2rtlil generated wire signedness | Zachary Snow | 2020-12-22 | 1 | -0/+1 | |
| | | | ||||||
| * | | Merge pull request #2476 from zachjs/const-arg-width | whitequark | 2020-12-23 | 1 | -0/+8 | |
| |\ \ | |/ |/| | Fix constants bound to single bit arguments (fixes #2383) | |||||
| | * | Fix constants bound to single bit arguments (fixes #2383) | Zachary Snow | 2020-12-22 | 1 | -0/+8 | |
| | | | ||||||
| * | | Merge pull request #2479 from zachjs/const-arg-hint | whitequark | 2020-12-22 | 1 | -0/+5 | |
| |\ \ | | | | | | | Allow constant function calls in constant function arguments | |||||
| | * | | Allow constant function calls in constant function arguments | Zachary Snow | 2020-12-07 | 1 | -0/+5 | |
| | |/ | ||||||
| * / | Sign extend port connections where necessary | Zachary Snow | 2020-12-18 | 1 | -2/+24 | |
| |/ | | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265 | |||||
| * | Merge pull request #2456 from Zottel/master | whitequark | 2020-12-02 | 1 | -0/+1 | |
| |\ | | | | | Return correct modname when found in cache. | |||||
| | * | Return correct modname when found in cache. | Julius Roob | 2020-11-26 | 1 | -0/+1 | |
| | | | ||||||
| * | | Bump required Verific version | Miodrag Milanovic | 2020-12-02 | 1 | -1/+1 | |
| | | | ||||||
| * | | Fix SYNTHESIS always being defined in Verilog frontend | georgerennie | 2020-12-01 | 2 | -1/+3 | |
| |/ | ||||||
| * | rtlil: remove dotted identifiers. | whitequark | 2020-11-25 | 1 | -1/+0 | |
| | | | | | No one knows where they came from and they never did anything useful. | |||||
| * | Update verific version | Miodrag Milanovic | 2020-10-30 | 1 | -1/+1 | |
| | | ||||||
| * | Fix argument handling in connect_rpc | Claire Xenia Wolf | 2020-10-19 | 1 | -1/+2 | |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com> | |||||
| * | extend verific library API for formal apps and generators | Miodrag Milanovic | 2020-10-12 | 1 | -15/+83 | |
| | | ||||||
| * | Update required Verific version | Miodrag Milanović | 2020-10-05 | 1 | -1/+1 | |
| | | ||||||
| * | Ignore empty parameters in Verilog module instantiations | Claire Xenia Wolf | 2020-10-01 | 1 | -0/+3 | |
| | | | | | | | Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com> | |||||
| * | Merge pull request #2378 from udif/pr_dollar_high_low | clairexen | 2020-10-01 | 3 | -31/+98 | |
| |\ | | | | | Added $high(), $low(), $left(), $right() | |||||
| | * | We can now handle array slices (e.g. $size(x[1]) etc. ) | Udi Finkelstein | 2020-09-17 | 1 | -7/+6 | |
| | | | ||||||
| | * | Fixed comments, removed debug message | Udi Finkelstein | 2020-09-16 | 1 | -5/+5 | |
| | | | ||||||
| | * | Added $high(), $low(), $left(), $right() | Udi Finkelstein | 2020-09-15 | 3 | -30/+98 | |
| | | | ||||||
| * | | use sha1 for parameter list in case if they contain spaces | Miodrag Milanovic | 2020-09-30 | 1 | -2/+18 | |
| | | | ||||||
| * | | Better error for unsupported SVA sequence | Miodrag Milanovic | 2020-09-18 | 1 | -2/+8 | |
| | | | ||||||
| * | | Merge pull request #2329 from antmicro/arrays-fix-multirange-size | clairexen | 2020-09-17 | 1 | -2/+11 | |
| |\ \ | | | | | | | Rewrite multirange arrays sizes [n] as [n-1:0] | |||||
| | * | | Rewrite multirange arrays sizes [n] as [n-1:0] | Lukasz Dalek | 2020-08-03 | 1 | -2/+11 | |
| | | | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | |||||
| * | | | Merge pull request #2330 from antmicro/arrays-fix-multirange-access | clairexen | 2020-09-17 | 1 | -1/+1 | |
| |\ \ \ | |_|/ |/| | | Fix unsupported subarray access detection | |||||
| | * | | Fix subarray access condition | Lukasz Dalek | 2020-08-03 | 1 | -1/+1 | |
| | |/ | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> | |||||
| * | | Use latest verific | Miodrag Milanovic | 2020-09-02 | 1 | -1/+1 | |
| | | | ||||||
| * | | Merge pull request #2352 from zachjs/const-func-localparam | clairexen | 2020-09-01 | 1 | -0/+12 | |
| |\ \ | | | | | | | Allow localparams in constant functions | |||||
| | * | | Allow localparams in constant functions | Zachary Snow | 2020-08-20 | 1 | -0/+12 | |
| | | | | ||||||
| * | | | Merge pull request #2366 from zachjs/library-format | clairexen | 2020-09-01 | 1 | -0/+11 | |
| |\ \ \ | | | | | | | | | Simple support for %l format specifier | |||||
| | * | | | Simple support for %l format specifier | Zachary Snow | 2020-08-29 | 1 | -0/+11 | |
| | |/ / | | | | | | | | | | | | | Yosys doesn't support libraries, so this provides the same behavior as %m, as some other tools have opted to do. | |||||
| * | | | Merge pull request #2353 from zachjs/top-scope | clairexen | 2020-09-01 | 1 | -0/+7 | |
| |\ \ \ | | | | | | | | | Module name scope support | |||||
| | * | | | Module name scope support | Zachary Snow | 2020-08-20 | 1 | -0/+7 | |
| | |/ / | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |