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| author | Zachary Snow <zach@zachjs.com> | 2020-12-31 16:14:35 -0700 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2020-12-31 16:17:13 -0700 |
| commit | 75abd908294c599c9987978175b46196146c9d1d (patch) | |
| tree | d8aac5e136b6e68ef265c16ca49461527d78df19 /frontends | |
| parent | 48d0aeb09483283c46491448304bf04865e176f5 (diff) | |
| download | yosys-75abd908294c599c9987978175b46196146c9d1d.tar.gz yosys-75abd908294c599c9987978175b46196146c9d1d.tar.bz2 yosys-75abd908294c599c9987978175b46196146c9d1d.zip | |
sv: complete support for implied task/function port directions
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 678ce6c87..6c4b06d7f 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -884,7 +884,11 @@ task_func_args: task_func_port: attr wire_type range { + bool prev_was_input = true; + bool prev_was_output = false; if (albuf) { + prev_was_input = astbuf1->is_input; + prev_was_output = astbuf1->is_output; delete astbuf1; if (astbuf2 != NULL) delete astbuf2; @@ -893,6 +897,12 @@ task_func_port: albuf = $1; astbuf1 = $2; astbuf2 = checkRange(astbuf1, $3); + if (!astbuf1->is_input && !astbuf1->is_output) { + if (!sv_mode) + frontend_verilog_yyerror("task/function argument direction missing"); + astbuf1->is_input = prev_was_input; + astbuf1->is_output = prev_was_output; + } } wire_name | { if (!astbuf1) { |