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| author | Claire Xenia Wolf <claire@symbioticeda.com> | 2020-10-01 18:26:53 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@symbioticeda.com> | 2020-10-01 18:27:16 +0200 |
| commit | 46f0932c4c61aca3ab5332f99a4a60d110b52191 (patch) | |
| tree | c33b214a81a2967dd550b93339ba1b9cf0596a07 /frontends | |
| parent | 7e2fc2eaeb70179c8da3e5dc8be800f486d5b912 (diff) | |
| download | yosys-46f0932c4c61aca3ab5332f99a4a60d110b52191.tar.gz yosys-46f0932c4c61aca3ab5332f99a4a60d110b52191.tar.bz2 yosys-46f0932c4c61aca3ab5332f99a4a60d110b52191.zip | |
Ignore empty parameters in Verilog module instantiations
Fixes #2394
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8e5236639..678ce6c87 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1891,6 +1891,9 @@ cell_parameter: astbuf1->children.push_back(node); node->children.push_back($1); } | + '.' TOK_ID '(' ')' { + // just ignore empty parameters + } | '.' TOK_ID '(' expr ')' { AstNode *node = new AstNode(AST_PARASET); node->str = *$2; |