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* frontend: json: parse negative valuesKarol Gugala2021-02-231-2/+10
| | | | Signed-off-by: Karol Gugala <kgugala@antmicro.com>
* Merge pull request #2586 from zachjs/tern-recursewhitequark2021-02-213-19/+119
|\ | | | | verilog: support recursive functions using ternary expressions
| * verilog: support recursive functions using ternary expressionsZachary Snow2021-02-123-19/+119
| | | | | | | | | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-191-1/+10
| | | | | | | | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
* | Merge pull request #2574 from dh73/masterClaire Xen2021-02-151-0/+5
|\ \ | |/ |/| Accept disable case for SVA liveness properties.
| * Accept disable case for SVA liveness properties.Diego H2021-02-041-0/+5
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* | Ganulate Verific supportMiodrag Milanovic2021-02-121-8/+16
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* | Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-112-72/+82
|\ \ | | | | | | verilog: refactored constant function evaluation
| * | verilog: refactored constant function evaluationZachary Snow2021-02-042-72/+82
| |/ | | | | | | | | | | | | | | | | | | | | Elaboration now attempts constant evaluation of any function call with only constant arguments, regardless of the context or contents of the function. This removes the concept of "recommended constant evaluation" which previously applied to functions with `for` loops or which were (sometimes erroneously) identified as recursive. Any function call in a constant context (e.g., `localparam`) or which contains a constant-only procedural construct (`while` or `repeat`) in its body will fail as before if constant evaluation does not succeed.
* | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
|\ \ | | | | | | verlog: allow shadowing module ports within generate blocks
| * | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
|/ / | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-051-1/+5
| | | | | | | | | | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* | Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
|/ | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-043-148/+169
|\ | | | | verilog: significant block scoping improvements
| * verilog: significant block scoping improvementsZachary Snow2021-01-313-148/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | Require latest Verific buildMiodrag Milanovic2021-01-301-1/+1
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* | ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
| | | | | | | | | | | | The first child of AST_CASE is the case expression, it's subsequent childrean that are AST_COND* and can be used to discriminate the type of the case.
* | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-1/+5
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* Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-251-1/+0
|\ | | | | verilog: allow spaces in macro arguments
| * verilog: allow spaces in macro argumentsZachary Snow2021-01-201-1/+0
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* | dpi: Support for chandle typeDavid Shah2021-01-231-1/+16
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
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* | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ ↵Claire Xenia Wolf2021-01-201-18/+18
| | | | | | | | | | | | flavored Verific Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
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* Fix input/output attributes when resolving typedef of wireKamil Rakoczy2021-01-181-0/+3
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
| | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Merge pull request #2518 from zachjs/recursionwhitequark2021-01-012-8/+28
|\ | | | | verilog: improved support for recursive functions
| * verilog: improved support for recursive functionsZachary Snow2020-12-312-8/+28
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* | sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
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* Fix elaboration of whole memory words used as indicesZachary Snow2020-12-261-1/+8
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* Fix constants bound to redeclared function argsZachary Snow2020-12-261-5/+16
| | | | | | | | The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
* Merge pull request #2501 from zachjs/genrtlil-tern-signwhitequark2020-12-231-0/+1
|\ | | | | genrtlil: fix mux2rtlil generated wire signedness
| * genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-0/+1
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* | Merge pull request #2476 from zachjs/const-arg-widthwhitequark2020-12-231-0/+8
|\ \ | |/ |/| Fix constants bound to single bit arguments (fixes #2383)
| * Fix constants bound to single bit arguments (fixes #2383)Zachary Snow2020-12-221-0/+8
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* | Merge pull request #2479 from zachjs/const-arg-hintwhitequark2020-12-221-0/+5
|\ \ | | | | | | Allow constant function calls in constant function arguments
| * | Allow constant function calls in constant function argumentsZachary Snow2020-12-071-0/+5
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* / Sign extend port connections where necessaryZachary Snow2020-12-181-2/+24
|/ | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Merge pull request #2456 from Zottel/masterwhitequark2020-12-021-0/+1
|\ | | | | Return correct modname when found in cache.
| * Return correct modname when found in cache.Julius Roob2020-11-261-0/+1
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* | Bump required Verific versionMiodrag Milanovic2020-12-021-1/+1
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* | Fix SYNTHESIS always being defined in Verilog frontendgeorgerennie2020-12-012-1/+3
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* rtlil: remove dotted identifiers.whitequark2020-11-251-1/+0
| | | | No one knows where they came from and they never did anything useful.
* Update verific versionMiodrag Milanovic2020-10-301-1/+1
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* Fix argument handling in connect_rpcClaire Xenia Wolf2020-10-191-1/+2
| | | | Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* extend verific library API for formal apps and generatorsMiodrag Milanovic2020-10-121-15/+83
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* Update required Verific versionMiodrag Milanović2020-10-051-1/+1
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* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
| | | | | | Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* Merge pull request #2378 from udif/pr_dollar_high_lowclairexen2020-10-013-31/+98
|\ | | | | Added $high(), $low(), $left(), $right()
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