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Age
Files
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...
*
Add SVA support for sequence OR
Clifford Wolf
2018-03-03
1
-22
/
+33
*
Fix handling of SVA "until seq.triggered" properties
Clifford Wolf
2018-03-02
1
-7
/
+25
*
Update SVA cheat sheet in verificsva.cc
Clifford Wolf
2018-03-02
1
-2
/
+4
*
Fix in Verific SVA importer handling of until_with
Clifford Wolf
2018-03-01
1
-7
/
+5
*
Fixes and improvements in Verific SVA importer
Clifford Wolf
2018-03-01
3
-83
/
+136
*
Add $rose/$fell support to Verific bindings
Clifford Wolf
2018-03-01
1
-3
/
+22
*
Add support for PRIM_SVA_UNTIL to new SVA importer
Clifford Wolf
2018-02-28
1
-0
/
+27
*
Add DFSM generator to verific SVA importer
Clifford Wolf
2018-02-28
1
-19
/
+272
*
Continue refactoring of Verific SVA importer code
Clifford Wolf
2018-02-28
3
-671
/
+172
*
Major redesign of Verific SVA importer
Clifford Wolf
2018-02-27
1
-5
/
+573
*
Add handling of verific OPER_REDUCE_NOR
Clifford Wolf
2018-02-26
1
-0
/
+6
*
Add handling of verific OPER_SELECTOR and OPER_WIDE_SELECTOR
Clifford Wolf
2018-02-26
1
-0
/
+13
*
Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX
Clifford Wolf
2018-02-26
1
-0
/
+25
*
Add "SVA syntax cheat sheet" comment to verificsva.cc
Clifford Wolf
2018-02-26
1
-0
/
+34
*
Add $allconst and $allseq cell types
Clifford Wolf
2018-02-23
3
-4
/
+6
*
Add Verific SVA support for ranges in repetition operator
Clifford Wolf
2018-02-22
1
-5
/
+26
*
Add support for SVA throughout via Verific
Clifford Wolf
2018-02-21
1
-2
/
+6
*
Add support for SVA sequence concatenation ranges via verific
Clifford Wolf
2018-02-18
1
-16
/
+124
*
Add support for SVA until statements via Verific
Clifford Wolf
2018-02-18
2
-34
/
+119
*
Move Verific SVA importer to extra C++ source file
Clifford Wolf
2018-02-18
4
-1279
/
+1370
*
Merge Verific SVA preprocessor and SVA importer
Clifford Wolf
2018-02-18
1
-79
/
+44
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2018-02-16
1
-0
/
+6
|
\
|
*
Improve handling of "bus" pins in liberty front-end (some files use bus.pin.d...
Clifford Wolf
2018-02-15
1
-0
/
+6
*
|
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
Clifford Wolf
2018-02-15
1
-1
/
+1
|
/
*
Fix single-bit $stable handling in verific front-end
Clifford Wolf
2018-02-01
1
-0
/
+22
*
Add Verific attribute handling for assert/assume/cover/live/fair cells
Clifford Wolf
2018-01-31
1
-10
/
+16
*
Fix permissions on verific vdb files
Clifford Wolf
2018-01-28
1
-0
/
+1
*
Fixed handling of synchronous and asynchronous assertion/assumption/cover in ...
Clifford Wolf
2018-01-23
1
-27
/
+29
*
Add support for "yosys -E"
Clifford Wolf
2018-01-07
2
-2
/
+5
*
Merge pull request #479 from Fatsie/latch_without_data
Clifford Wolf
2018-01-05
1
-4
/
+23
|
\
|
*
Some standard cell libraries include a latch with only set/reset.
Staf Verhaegen
2018-01-03
1
-4
/
+23
*
|
Bugfix in hierarchy handling of blackbox module ports
Clifford Wolf
2018-01-05
2
-2
/
+2
|
/
*
Bugfix in verilog_defaults argument parser
Clifford Wolf
2017-12-24
1
-1
/
+1
*
Add support for Verific PRIM_SVA_NOT properties
Clifford Wolf
2017-12-10
1
-10
/
+25
*
Add Verific OPER_SVA_STABLE support
Clifford Wolf
2017-12-10
1
-2
/
+32
*
Refactoring Verific SVA rewriter
Clifford Wolf
2017-12-10
1
-62
/
+70
*
Fix error handling for nested always/initial
Clifford Wolf
2017-12-02
2
-0
/
+5
*
Add Verilog "automatic" keyword (ignored in synthesis)
Clifford Wolf
2017-11-23
2
-13
/
+18
*
Accept real-valued delay values
Clifford Wolf
2017-11-18
1
-0
/
+1
*
Accommodate Windows-style paths during include-file processing.
William D. Jones
2017-11-14
1
-4
/
+20
*
Remove vhdl2verilog
Clifford Wolf
2017-10-25
2
-184
/
+0
*
Remove all PSL support code from verific.cc
Clifford Wolf
2017-10-20
1
-179
/
+17
*
Add "verific -vlog-libdir"
Clifford Wolf
2017-10-13
1
-0
/
+12
*
Add "verific -vlog-incdir" and "verific -vlog-define"
Clifford Wolf
2017-10-13
1
-0
/
+35
*
Update Verific README
Clifford Wolf
2017-10-13
1
-0
/
+7
*
Add Verific fairness/liveness support
Clifford Wolf
2017-10-12
1
-11
/
+32
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2017-10-10
1
-16
/
+5
|
\
|
*
Remove some dead code
Clifford Wolf
2017-10-10
1
-15
/
+0
|
*
Allow $past, $stable, $rose, $fell in $global_clock blocks
Clifford Wolf
2017-10-10
1
-1
/
+5
*
|
Start work on pre-processor for Verific SVA properties
Clifford Wolf
2017-10-10
1
-10
/
+153
|
/
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