Add handling of verific OPER_NTO1MUX and OPER_WIDE_NTO1MUX

Signed-off-by: Clifford Wolf <clifford@clifford.at>

1 files changed, 25 insertions, 0 deletions

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 3d24b64cd..4c28d4c43 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -544,6 +544,31 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		return true;
 	}
 
+	if (inst->Type() == OPER_NTO1MUX) {
+		module->addShr(inst_name, IN2, IN1, net_map_at(inst->GetOutput()));
+		return true;
+	}
+
+	if (inst->Type() == OPER_WIDE_NTO1MUX)
+	{
+		SigSpec data = IN2, out = OUT;
+
+		int wordsize_bits = ceil_log2(GetSize(out));
+		int wordsize = 1 << wordsize_bits;
+
+		SigSpec sel = {IN1, SigSpec(State::S0, wordsize_bits)};
+
+		SigSpec padded_data;
+		for (int i = 0; i < GetSize(data); i += GetSize(out)) {
+			SigSpec d = data.extract(i, GetSize(out));
+			d.extend_u0(wordsize);
+			padded_data.append(d);
+		}
+
+		module->addShr(inst_name, padded_data, sel, out);
+		return true;
+	}
+
 	if (inst->Type() == OPER_WIDE_TRI) {
 		module->addMux(inst_name, RTLIL::SigSpec(RTLIL::State::Sz, inst->OutputSize()), IN, net_map_at(inst->GetControl()), OUT);
 		return true;