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| author | Clifford Wolf <clifford@clifford.at> | 2017-10-13 20:12:51 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-10-13 20:12:51 +0200 |
| commit | e7a3c47cc793eaacff3b3bf0e996944f6963a7a8 (patch) | |
| tree | 57c324336221ba900a0bae5a3c0083e6f1c55742 /frontends | |
| parent | 05068af88041d8fffbece6ec94f240c7ae3e4f54 (diff) | |
| download | yosys-e7a3c47cc793eaacff3b3bf0e996944f6963a7a8.tar.gz yosys-e7a3c47cc793eaacff3b3bf0e996944f6963a7a8.tar.bz2 yosys-e7a3c47cc793eaacff3b3bf0e996944f6963a7a8.zip | |
Add "verific -vlog-incdir" and "verific -vlog-define"
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/verific/verific.cc | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index e77931528..f8c1dcd0a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1851,6 +1851,16 @@ struct VerificPass : public Pass { log("Load the specified VHDL files into Verific.\n"); log("\n"); log("\n"); + log(" verific -vlog-incdir <directory>..\n"); + log("\n"); + log("Add Verilog include directories.\n"); + log("\n"); + log("\n"); + log(" verific -vlog-define <macro>[=<value>]..\n"); + log("\n"); + log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n"); + log("\n"); + log("\n"); log(" verific -import [options] <top-module>..\n"); log("\n"); log("Elaborate the design for the specified top modules, import to Yosys and\n"); @@ -1909,6 +1919,8 @@ struct VerificPass : public Pass { Message::RegisterCallBackMsg(msg_func); RuntimeFlags::SetVar("db_allow_external_nets", 1); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); + veri_file::DefineCmdLineMacro("VERIFIC"); + veri_file::DefineCmdLineMacro("SYNTHESIS"); const char *release_str = Message::ReleaseString(); time_t release_time = Message::ReleaseDate(); @@ -1924,6 +1936,27 @@ struct VerificPass : public Pass { int argidx = 1; + if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") { + for (argidx++; argidx < GetSize(args); argidx++) + veri_file::AddIncludeDir(args[argidx].c_str()); + goto check_error; + } + + if (GetSize(args) > argidx && args[argidx] == "-vlog-define") { + for (argidx++; argidx < GetSize(args); argidx++) { + string name = args[argidx]; + size_t equal = name.find('='); + if (equal != std::string::npos) { + string value = name.substr(equal+1); + name = name.substr(0, equal); + veri_file::DefineCmdLineMacro(name.c_str(), value.c_str()); + } else { + veri_file::DefineCmdLineMacro(name.c_str()); + } + } + goto check_error; + } + if (GetSize(args) > argidx && args[argidx] == "-vlog95") { for (argidx++; argidx < GetSize(args); argidx++) if (!veri_file::Analyze(args[argidx].c_str(), veri_file::VERILOG_95)) @@ -2139,6 +2172,8 @@ struct VerificPass : public Pass { nl_done.insert(nl); } + veri_file::Reset(); + vhdl_file::Reset(); Libset::Reset(); goto check_error; } |