aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
Commit message (Collapse)AuthorAgeFilesLines
* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-072-19/+19
|
* Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-38/+36
|\
| * Merge pull request #1252 from YosysHQ/clifford/fix1231Clifford Wolf2019-08-071-15/+2
| |\ | | | | | | Fix handling of functions/tasks without top-level begin-end block
| | * Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-071-23/+34
| |\ \ | | |/ | |/| Improved JSON attr/param encoding
| | * Update JSON front-end to process new attr/param encodingClifford Wolf2019-08-011-23/+34
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | stoi -> atoiEddie Hung2019-08-073-5/+5
| | |
* | | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
| | |
* | | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-063-5/+5
| | |
* | | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-061-16/+16
| | |
* | | Use State::S{0,1}Eddie Hung2019-08-061-1/+1
|/ /
* | Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-021-0/+4
|\ \ | |/ |/| Fix formatting for msys2 mingw build
| * Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-0/+4
| |
* | Merge pull request #1233 from YosysHQ/clifford/deferClifford Wolf2019-07-311-1/+2
|\ \ | |/ |/| Call "read_verilog" with -defer from "read"
| * Call "read_verilog" with -defer from "read"Clifford Wolf2019-07-291-1/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
|
* Fix typo, double "of"Miodrag Milanovic2019-07-161-1/+1
|
* Fix missing semicolon in Windows-specific code in aigerparse.cc.William D. Jones2019-07-141-2/+2
| | | | Signed-off-by: William D. Jones <thor0505@comcast.net>
* genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
|
* Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parser changes are slightly awkward. Consider the following IL: process $0 <point 1> switch \foo <point 2> case 1'1 assign \bar \baz <point 3> ... case end end Before this commit, attributes are valid in <point 1>, and <point 3> iff it is immediately followed by a `switch`. (They are essentially attached to the switch.) But, after this commit, and because switch cases do not have an ending delimiter, <point 3> becomes ambiguous: the attribute could attach to either the following `case`, or to the following `switch`. This isn't expressible in LALR(1) and results in a reduce/reduce conflict. To address this, attributes inside processes are now valid anywhere inside the process: in <point 1> and <point 3> a part of case body, and in <point 2> as a separate rule. As a consequence, attributes can now precede `assign`s, which is made illegal in the same way it is illegal to attach attributes to `connect`. Attributes are tracked separately from the parser state, so this does not affect collection of attributes at all, other than allowing them on `case`s. The grammar change serves purely to allow attributes in more syntactic places.
* Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-031-81/+14
|\ | | | | Improve specify dummy parser
| * Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-79/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131Clifford Wolf2019-06-261-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix read_verilog assert/assume/etc on default case label, fixes ↵Clifford Wolf2019-07-021-0/+2
| | | | | | | | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Replace log_assert() with meaningful log_error()Eddie Hung2019-06-281-1/+5
| |
* | Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-31/+37
| |
* | Remove unneeded includeEddie Hung2019-06-271-3/+0
| |
* | Merge origin/masterEddie Hung2019-06-271-1/+1
| |
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-241-0/+12
|\|
| * Add upto and offset to JSON portsMiodrag Milanovic2019-06-211-0/+12
| |
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-213-6/+19
|\|
| * Fix typoMiodrag Milanovic2019-06-211-1/+1
| |
| * Added JSON upto and offsetClifford Wolf2019-06-211-0/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-211-0/+1
| |\ | | | | | | Make genvar a signed type
| | * Make genvar a signed typeEddie Hung2019-06-201-0/+1
| | |
| * | Maintain "is_unsized" state of constantsEddie Hung2019-06-201-6/+6
| |/
* | Reduce log_debug spam in parse_xaiger()Eddie Hung2019-06-211-16/+19
| |
* | Workaround issues exposed by gcc-4.8Eddie Hung2019-06-211-0/+7
| |
* | Fix broken abc9.v test due to inout being 1'bxEddie Hung2019-06-201-3/+10
| |
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-206-15/+77
|\|
| * Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-201-1/+7
| |\ | | | | | | | | | towoe-unpacked_arrays
| | * Unpacked array declaration using sizeTobias Wölfel2019-06-191-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
| * | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-195-9/+44
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add defaultvalue attributeClifford Wolf2019-06-191-0/+11
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
| |/ | | | | | | (within always/initial blocks)
* | Fix issue with part of PI being 1'bxEddie Hung2019-06-201-4/+6
| |
* | CleanupEddie Hung2019-06-161-20/+1
| |