Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Merge pull request #1551 from whitequark/manual-cell-operands | Clifford Wolf | 2019-12-05 | 1 | -5/+5 |
|\ | | | | | Clarify semantics of comb cells, in particular shifts | ||||
| * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. | whitequark | 2019-12-04 | 1 | -5/+5 |
| | | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs. | ||||
* | | read_ilang: do bounds checking on bit indices | Marcin Kościelnicki | 2019-11-27 | 1 | -0/+4 |
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* | Add Verific support for SVA nexttime properties | Clifford Wolf | 2019-11-22 | 1 | -0/+22 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Improve handling of verific primitives in "verific -import -V" mode | Clifford Wolf | 2019-11-22 | 1 | -2/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add Verific SVA support for "always" properties | Clifford Wolf | 2019-11-22 | 1 | -5/+15 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 2 | -5/+40 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Correctly treat empty modules as blackboxes in Verific | Clifford Wolf | 2019-11-20 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Do not rename VHDL entities to "entity(impl)" when they are top modules | Clifford Wolf | 2019-11-20 | 2 | -5/+8 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add check for valid macro names in macro definitions | Clifford Wolf | 2019-11-07 | 1 | -7/+11 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Improve naming scheme for (VHDL) modules imported from Verific | Clifford Wolf | 2019-10-24 | 1 | -3/+26 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "verific -L" | Clifford Wolf | 2019-10-24 | 1 | -1/+12 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add "verilog_defines -list" and "verilog_defines -reset" | Clifford Wolf | 2019-10-21 | 1 | -0/+16 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix handling of "restrict" in Verific front-end | Clifford Wolf | 2019-10-21 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix parsing of .cname BLIF statements | Clifford Wolf | 2019-10-16 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add .blackbox support to blif front-end | Clifford Wolf | 2019-10-16 | 1 | -0/+6 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 5 | -20/+187 |
|\ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | frontends/ast: code style | David Shah | 2019-10-03 | 1 | -2/+1 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Fix typedefs in blocks | David Shah | 2019-10-03 | 1 | -2/+2 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Disambiguate interface ports | David Shah | 2019-10-03 | 1 | -3/+19 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Fix memories of typedefs | David Shah | 2019-10-03 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Add %expect | David Shah | 2019-10-03 | 1 | -0/+1 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Add support for memories of a typedef | David Shah | 2019-10-03 | 1 | -6/+20 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Add support for memory typedefs | David Shah | 2019-10-03 | 2 | -3/+34 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Fix typedefs in packages | David Shah | 2019-10-03 | 1 | -4/+10 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Fix typedef parameters | David Shah | 2019-10-03 | 2 | -6/+48 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | sv: Switch parser to glr, prep for typedef | David Shah | 2019-10-03 | 5 | -11/+89 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 1 | -4/+4 |
|\ \ | | | | | | | Rename abc_* names/attributes to more precisely be abc9_* | ||||
| * | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -4/+4 |
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* | | | Fixes for MSVC build | Miodrag Milanovic | 2019-10-04 | 1 | -2/+6 |
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* | | Merge pull request #1419 from YosysHQ/eddie/lazy_derive | Clifford Wolf | 2019-10-03 | 2 | -35/+59 |
|\ \ | |/ |/| | module->derive() to be lazy and not touch ast if already derived | ||||
| * | Fix for svinterfaces | Eddie Hung | 2019-09-30 | 1 | -2/+8 |
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| * | module->derive() to be lazy and not touch ast if already derived | Eddie Hung | 2019-09-30 | 2 | -33/+51 |
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* | | Define environ, fixes #1424 | Miodrag Milanovic | 2019-10-01 | 1 | -0/+2 |
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* | Merge pull request #1406 from whitequark/connect_rpc | whitequark | 2019-09-30 | 2 | -0/+591 |
|\ | | | | | rpc: new frontend | ||||
| * | rpc: new frontend. | whitequark | 2019-09-30 | 2 | -0/+591 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design. | ||||
* | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 1 | -2/+6 |
|\ \ | | | | | | | Open aig frontend as binary file | ||||
| * | | Fix reading aig files on windows | Miodrag Milanovic | 2019-09-29 | 1 | -1/+5 |
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| * | | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 1 | -1/+1 |
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* / | Force $inout.out ports to begin with '$' to indicate internal | Eddie Hung | 2019-09-23 | 1 | -2/+2 |
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* | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵ | Clifford Wolf | 2019-09-20 | 2 | -18/+30 |
| | | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext | Eddie Hung | 2019-09-18 | 1 | -1/+1 |
|\ | | | | | peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells | ||||
| * | Revert "parse_xaiger() to do "clean -purge"" | Eddie Hung | 2019-09-04 | 1 | -1/+1 |
| | | | | | | | | This reverts commit 5d16bf831688ff665b0ec2abd6835b71320b2db5. | ||||
* | | Fix handling of range selects on loop variables, fixes #1372 | Clifford Wolf | 2019-09-16 | 1 | -2/+9 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Fix handling of z_digit "?" and fix optimization of cmp with "z" | Clifford Wolf | 2019-09-13 | 1 | -5/+1 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Fix lexing of integer literals without radix | Clifford Wolf | 2019-09-13 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Fix lexing of integer literals, fixes #1364 | Clifford Wolf | 2019-09-12 | 2 | -3/+3 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge pull request #1312 from YosysHQ/xaig_arrival | Eddie Hung | 2019-09-05 | 1 | -14/+25 |
|\ \ | | | | | | | Allow arrival times of sequential outputs to be specified to abc9 | ||||
| * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-09-04 | 1 | -0/+7 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
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