| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Big rework; flop info now mostly in cells_sim.v | Eddie Hung | 2019-09-28 | 1 | -6/+13 |
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| * | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-27 | 5 | -35/+73 |
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| | * | Fix handling of read_verilog config in AstModule::reprocess_module(), fixes ↵ | Clifford Wolf | 2019-09-20 | 2 | -18/+30 |
| | | | | | | | | | | | | | #1360 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext | Eddie Hung | 2019-09-18 | 1 | -1/+1 |
| | |\ | | | | | | | peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells | ||||
| | | * | Revert "parse_xaiger() to do "clean -purge"" | Eddie Hung | 2019-09-04 | 1 | -1/+1 |
| | | | | | | | | | | | | | This reverts commit 5d16bf831688ff665b0ec2abd6835b71320b2db5. | ||||
| | * | | Fix handling of range selects on loop variables, fixes #1372 | Clifford Wolf | 2019-09-16 | 1 | -2/+9 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Fix handling of z_digit "?" and fix optimization of cmp with "z" | Clifford Wolf | 2019-09-13 | 1 | -5/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Fix lexing of integer literals without radix | Clifford Wolf | 2019-09-13 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Fix lexing of integer literals, fixes #1364 | Clifford Wolf | 2019-09-12 | 2 | -3/+3 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge pull request #1312 from YosysHQ/xaig_arrival | Eddie Hung | 2019-09-05 | 1 | -14/+25 |
| | |\ \ | | | | | | | | | Allow arrival times of sequential outputs to be specified to abc9 | ||||
| | | * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-09-04 | 1 | -0/+7 |
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| | | * | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
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| | | * \ \ | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 1 | -0/+5 |
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| | * | \ \ \ | Merge pull request #1350 from YosysHQ/clifford/fixsby59 | Clifford Wolf | 2019-09-05 | 1 | -7/+18 |
| | |\ \ \ \ \ | | |_|_|_|/ | |/| | | | | Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)" | ||||
| | | * | | | | Properly construct $live and $fair cells from "if (...) assume/assert ↵ | Clifford Wolf | 2019-09-02 | 1 | -7/+18 |
| | | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (s_eventually ...)" Fixes https://github.com/YosysHQ/SymbiYosys/issues/59 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | | Merge remote-tracking branch 'origin/master' into eddie/deferred_top | Eddie Hung | 2019-09-03 | 1 | -1/+1 |
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| | | * | | | parse_xaiger() to do "clean -purge" | Eddie Hung | 2019-08-29 | 1 | -1/+1 |
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| | * | | | Remove newline | Eddie Hung | 2019-08-29 | 1 | -1/+0 |
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| | * | | | Restore non-deferred code, deferred case to ignore non constant attr | Eddie Hung | 2019-08-29 | 1 | -5/+12 |
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| | * | | | read_verilog -defer should still populate module attributes | Eddie Hung | 2019-08-28 | 1 | -5/+6 |
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| | * | | Do not propagate mem2reg attribute through to result | Eddie Hung | 2019-08-22 | 1 | -1/+2 |
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| | * | | mem2reg to preserve user attributes and src | Eddie Hung | 2019-08-21 | 1 | -0/+4 |
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| * | | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 1 | -2/+33 |
| | |/ |/| | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c. | ||||
| * | | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -33/+2 |
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| * | | Use abc_{map,unmap,model}.v | Eddie Hung | 2019-08-20 | 1 | -31/+10 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 1 | -1/+4 |
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| | * | Merge pull request #1308 from jakobwenzel/real_params | Clifford Wolf | 2019-08-20 | 1 | -1/+4 |
| | |\ | | | | | | | Handle real values when deriving ast modules | ||||
| | | * | handle real values when deriving ast modules | Jakob Wenzel | 2019-08-19 | 1 | -1/+4 |
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| | * | | Fix typo | Eddie Hung | 2019-08-19 | 1 | -1/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-19 | 3 | -14/+11 |
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| | * | Merge branch 'master' into eddie/pr1266_again | whitequark | 2019-08-18 | 4 | -15/+12 |
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| | | * | Merge pull request #1283 from YosysHQ/clifford/fix1255 | Clifford Wolf | 2019-08-17 | 2 | -13/+10 |
| | | |\ | | | | | | | | | Fix various NDEBUG compiler warnings | ||||
| | | | * | Fix erroneous ifndef-NDEBUG in verific.cc | Clifford Wolf | 2019-08-17 | 1 | -3/+1 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | | | * | Remove unused variable | Eddie Hung | 2019-08-16 | 1 | -5/+0 |
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| | | | * | Fix various NDEBUG compiler warnings, closes #1255 | Clifford Wolf | 2019-08-13 | 2 | -9/+13 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
| | | |/ | |/| | | | | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | ||||
| * | | | Set abc_flop and use it in toposort | Eddie Hung | 2019-08-19 | 1 | -0/+1 |
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| * | | | Merge branch 'eddie/abc9_refactor' into xaig_dff | Eddie Hung | 2019-08-16 | 15 | -124/+172 |
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| | * | | Change signature of parse_blif to take IdString | Eddie Hung | 2019-08-15 | 2 | -2/+2 |
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| | * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 1 | -1/+1 |
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| | * | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 8 | -49/+49 |
| | |\ | | | | | | | Cleanup a few barnacles across codebase | ||||
| | | * | substr() -> compare() | Eddie Hung | 2019-08-07 | 5 | -12/+12 |
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| | | * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 2 | -19/+19 |
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| | | * | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 2 | -38/+36 |
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| | | * | | stoi -> atoi | Eddie Hung | 2019-08-07 | 3 | -5/+5 |
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| | | * | | IdString::str().substr() -> IdString::substr() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
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| | | * | | Use std::stoi instead of atoi(<str>.c_str()) | Eddie Hung | 2019-08-06 | 3 | -5/+5 |
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| | | * | | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-06 | 1 | -16/+16 |
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| | | * | | Use State::S{0,1} | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
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| | * | | | Merge pull request #1261 from YosysHQ/clifford/verific_init | Clifford Wolf | 2019-08-10 | 2 | -7/+60 |
| | |\ \ \ | | | | | | | | | | | Automatically prune init attributes in verific front-end | ||||
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index : iCE40/yosys | |
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