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| * | | verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-212-10/+30
* | | | frontend: json: parse negative valuesKarol Gugala2021-02-231-2/+10
* | | | Merge pull request #2586 from zachjs/tern-recursewhitequark2021-02-213-19/+119
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| * | | | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-123-19/+119
* | | | | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-191-1/+10
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* | | | Merge pull request #2574 from dh73/masterClaire Xen2021-02-151-0/+5
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| * | | Accept disable case for SVA liveness properties.Diego H2021-02-041-0/+5
* | | | Ganulate Verific supportMiodrag Milanovic2021-02-121-8/+16
* | | | Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-112-72/+82
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| * | | | verilog: refactored constant function evaluationZachary Snow2021-02-042-72/+82
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* | | | Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
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| * | | | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
* | | | | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
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* | | | genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-051-1/+5
* | | | Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
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* | | Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-043-148/+169
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| * | | verilog: significant block scoping improvementsZachary Snow2021-01-313-148/+169
* | | | Require latest Verific buildMiodrag Milanovic2021-01-301-1/+1
* | | | ast: fix dump_vlog display of casex/casezMarcelina Kościelnicka2021-01-291-2/+2
* | | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-1/+5
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* | | Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-251-1/+0
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| * | | verilog: allow spaces in macro argumentsZachary Snow2021-01-201-1/+0
* | | | dpi: Support for chandle typeDavid Shah2021-01-231-1/+16
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* | | Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
* | | Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavor...Claire Xenia Wolf2021-01-201-18/+18
* | | sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
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* | Fix input/output attributes when resolving typedef of wireKamil Rakoczy2021-01-181-0/+3
* | Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
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* Merge pull request #2518 from zachjs/recursionwhitequark2021-01-012-8/+28
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| * verilog: improved support for recursive functionsZachary Snow2020-12-312-8/+28
* | sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
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* Fix elaboration of whole memory words used as indicesZachary Snow2020-12-261-1/+8
* Fix constants bound to redeclared function argsZachary Snow2020-12-261-5/+16
* Merge pull request #2501 from zachjs/genrtlil-tern-signwhitequark2020-12-231-0/+1
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| * genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-0/+1
* | Merge pull request #2476 from zachjs/const-arg-widthwhitequark2020-12-231-0/+8
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| * Fix constants bound to single bit arguments (fixes #2383)Zachary Snow2020-12-221-0/+8
* | Merge pull request #2479 from zachjs/const-arg-hintwhitequark2020-12-221-0/+5
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| * | Allow constant function calls in constant function argumentsZachary Snow2020-12-071-0/+5
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* / Sign extend port connections where necessaryZachary Snow2020-12-181-2/+24
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* Merge pull request #2456 from Zottel/masterwhitequark2020-12-021-0/+1
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| * Return correct modname when found in cache.Julius Roob2020-11-261-0/+1
* | Bump required Verific versionMiodrag Milanovic2020-12-021-1/+1
* | Fix SYNTHESIS always being defined in Verilog frontendgeorgerennie2020-12-012-1/+3
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* rtlil: remove dotted identifiers.whitequark2020-11-251-1/+0
* Update verific versionMiodrag Milanovic2020-10-301-1/+1
* Fix argument handling in connect_rpcClaire Xenia Wolf2020-10-191-1/+2
* extend verific library API for formal apps and generatorsMiodrag Milanovic2020-10-121-15/+83
* Update required Verific versionMiodrag Milanović2020-10-051-1/+1
* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
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