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| * | | | | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-072-19/+19
| * | | | | Merge remote-tracking branch 'origin/master' into eddie/cleanupEddie Hung2019-08-072-38/+36
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| * | | | | | stoi -> atoiEddie Hung2019-08-073-5/+5
| * | | | | | IdString::str().substr() -> IdString::substr()Eddie Hung2019-08-061-1/+1
| * | | | | | Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-063-5/+5
| * | | | | | RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-061-16/+16
| * | | | | | Use State::S{0,1}Eddie Hung2019-08-061-1/+1
* | | | | | | Merge pull request #1261 from YosysHQ/clifford/verific_initClifford Wolf2019-08-102-7/+60
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| * | | | | | | Automatically prune init attributes in verific front-end, fixes #1237Clifford Wolf2019-08-072-7/+60
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* | | | | | | Add __STDC_FORMAT_MACROS before <inttypes.h> as per @mithroEddie Hung2019-08-091-0/+1
* | | | | | | Allow whitebox modules to be overwrittenEddie Hung2019-08-071-1/+1
* | | | | | | Run "clean" on mapped_mod in its own designEddie Hung2019-08-072-24/+10
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* | | | | | Merge pull request #1252 from YosysHQ/clifford/fix1231Clifford Wolf2019-08-071-15/+2
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| * | | | | | Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
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* | | | | | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-071-23/+34
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| * | | | | Update JSON front-end to process new attr/param encodingClifford Wolf2019-08-011-23/+34
* | | | | | Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-021-0/+4
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| * | | | | Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-011-0/+4
* | | | | | Merge pull request #1233 from YosysHQ/clifford/deferClifford Wolf2019-07-311-1/+2
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| * | | | | Call "read_verilog" with -defer from "read"Clifford Wolf2019-07-291-1/+2
* | | | | | verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
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* | | | | initialize noblackbox and nowb in AstModule::cloneJakob Wenzel2019-07-221-0/+2
* | | | | Fix typo, double "of"Miodrag Milanovic2019-07-161-1/+1
* | | | | Fix missing semicolon in Windows-specific code in aigerparse.cc.William D. Jones2019-07-141-2/+2
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* | | | genrtlil: emit \src attribute on CaseRule.whitequark2019-07-081-0/+1
* | | | Allow attributes on individual switch cases in RTLIL.whitequark2019-07-081-4/+9
* | | | Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-031-81/+14
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| * | | Some cleanups in "ignore specify parser"Clifford Wolf2019-07-031-79/+5
| * | | Improve specify dummy parser, fixes #1144Clifford Wolf2019-06-281-2/+9
| * | | Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131Clifford Wolf2019-06-261-1/+1
* | | | Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi...Clifford Wolf2019-07-021-0/+2
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* | | Replace log_assert() with meaningful log_error()Eddie Hung2019-06-281-1/+5
* | | Refactor for one "abc_carry" attribute on moduleEddie Hung2019-06-271-31/+37
* | | Remove unneeded includeEddie Hung2019-06-271-3/+0
* | | Merge origin/masterEddie Hung2019-06-271-1/+1
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-241-0/+12
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| * | Add upto and offset to JSON portsMiodrag Milanovic2019-06-211-0/+12
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-213-6/+19
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| * | Fix typoMiodrag Milanovic2019-06-211-1/+1
| * | Added JSON upto and offsetClifford Wolf2019-06-211-0/+12
| * | Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-211-0/+1
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| | * | Make genvar a signed typeEddie Hung2019-06-201-0/+1
| * | | Maintain "is_unsized" state of constantsEddie Hung2019-06-201-6/+6
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* | | Reduce log_debug spam in parse_xaiger()Eddie Hung2019-06-211-16/+19
* | | Workaround issues exposed by gcc-4.8Eddie Hung2019-06-211-0/+7
* | | Fix broken abc9.v test due to inout being 1'bxEddie Hung2019-06-201-3/+10
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-206-15/+77
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| * | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...Clifford Wolf2019-06-201-1/+7
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| | * | Unpacked array declaration using sizeTobias Wölfel2019-06-191-1/+7
| * | | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-195-9/+44