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* Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
* Option to disable verific VHDL supportMiodrag Milanovic2021-10-202-11/+45
* Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
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| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
* | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* verific set db_infer_set_reset_registersMiodrag Milanovic2021-10-041-0/+1
* Specify minimum bison version 3.0+Zachary Snow2021-10-012-0/+4
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-241-0/+1
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| * Fix TOK_ID memory leak in for_initializationZachary Snow2021-09-231-0/+1
* | sv: support wand and wor of data typesZachary Snow2021-09-211-9/+12
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-4/+10
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* verilog: Squash flex-triggered warning.Marcelina Kościelnicka2021-09-131-0/+2
* update required verific versionMiodrag Milanovic2021-09-021-1/+1
* sv: support declaration in generate for initializationZachary Snow2021-08-311-1/+95
* sv: support declaration in procedural for initializationZachary Snow2021-08-301-1/+48
* Make Verific extensions optionalMiodrag Milanovic2021-08-201-1/+6
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-136-2/+193
* sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-121-11/+44
* Allow optional comma after last entry in enumMichael Singer2021-08-091-11/+12
* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
* Require latest verificMiodrag Milanovic2021-08-021-1/+1
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+8
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-282-4/+31
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-284-51/+83
* Update to latest verificMiodrag Milanovic2021-07-211-3/+3
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-165-4/+83
* sv: fix two struct access bugsZachary Snow2021-07-153-1/+10
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-122-6/+2
* Update to latest Verific with extensions for initial assertionsMiodrag Milanovic2021-07-091-14/+9
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-062-2/+11
* Merge pull request #2835 from YosysHQ/verific_commandClaire Xen2021-07-051-0/+61
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| * Add additional helpMiodrag Milanovic2021-07-051-0/+22
| * Support command files in VerificMiodrag Milanovic2021-06-161-0/+39
* | sv: fix up end label checkingZachary Snow2021-06-161-7/+18
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* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
* verilog: fix leaking ASTNodesXiretza2021-06-142-7/+15
* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-0925-25/+25
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| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0825-25/+25
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-083-13/+30
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-081-5/+42
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* sv: support tasks and functions within packagesZachary Snow2021-06-013-2/+22
* verilog: fix case expression sign and width handlingZachary Snow2021-05-253-12/+49
* sv: support remaining assignment operatorsZachary Snow2021-05-252-42/+41
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