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* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-251-14/+14
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-182-0/+88
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| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+21
| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-122-0/+68
* | ignore protect endprotectargama2018-10-161-0/+3
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* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
* Added support for ommited "parameter" in Verilog-2001 style parameter decl in...Clifford Wolf2018-09-231-3/+9
* Add "make coverage"Clifford Wolf2018-08-273-6/+5
* Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
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| * Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| * Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...Udi Finkelstein2018-08-201-10/+22
| * A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
* | Added -no_dump_ptr flag for AST dump options in 'read_verilog'Udi Finkelstein2018-08-231-1/+9
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* Merge pull request #591 from hzeller/virtual-overrideClifford Wolf2018-08-151-6/+6
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| * Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-6/+6
* | Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-152-2/+7
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| * | Modified errors into warningsUdi Finkelstein2018-06-051-0/+1
| * | This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-112-2/+6
* | | Merge pull request #562 from udif/pr_fix_illegal_port_declClifford Wolf2018-08-151-3/+6
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| * | Detect illegal port declaration, e.g input/output/inout keyword must be the f...Udi Finkelstein2018-06-061-3/+6
* | | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-201-5/+3
* | | Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-201-5/+3
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* | Support SystemVerilog `` extension for macrosJim Paris2018-05-171-1/+5
* | Skip spaces around macro argumentsJim Paris2018-05-171-0/+1
* | Replace -ignore_redef with -[no]overwriteClifford Wolf2018-05-031-6/+17
* | Support more character literalsDan Gisselquist2018-05-031-1/+9
* | Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-272-2/+170
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* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+3
* Add support for "yosys -E"Clifford Wolf2018-01-071-2/+4
* Bugfix in verilog_defaults argument parserClifford Wolf2017-12-241-1/+1
* Add Verilog "automatic" keyword (ignored in synthesis)Clifford Wolf2017-11-232-13/+18
* Accept real-valued delay valuesClifford Wolf2017-11-181-0/+1
* Accommodate Windows-style paths during include-file processing.William D. Jones2017-11-141-4/+20
* Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textboo...Udi Finkelstein2017-09-301-3/+5
* Minor coding style fixClifford Wolf2017-09-261-1/+1
* Merge branch 'master' of https://github.com/combinatorylogic/yosys into combi...Clifford Wolf2017-09-261-41/+69
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| * Adding support for string macros and macros with arguments after includecombinatorylogic2017-09-211-41/+69
* | Fix ignoring of simulation timings so that invalid module parameters cause sy...Clifford Wolf2017-09-262-4/+2
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* Add a paragraph about pre-defined macros to read_verilog help messageClifford Wolf2017-07-211-0/+4
* Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons...Clifford Wolf2017-06-071-0/+1
* Fix handling of Verilog ~& and ~| operatorsClifford Wolf2017-06-011-0/+8
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