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| author | Udi Finkelstein <github@udifink.com> | 2018-06-05 17:44:24 +0300 |
|---|---|---|
| committer | Unknown <github@udifink.com> | 2018-06-05 18:03:22 +0300 |
| commit | 73d426bc879087ca522ca595a8ba921b647fae27 (patch) | |
| tree | 29a18815bf8fdae5f20fa4762da31562eabe2829 /frontends/verilog | |
| parent | 80d9d15f1c4b73ee73172b06fd2c8c55703aea54 (diff) | |
| download | yosys-73d426bc879087ca522ca595a8ba921b647fae27.tar.gz yosys-73d426bc879087ca522ca595a8ba921b647fae27.tar.bz2 yosys-73d426bc879087ca522ca595a8ba921b647fae27.zip | |
Modified errors into warnings
No longer false warnings for memories and assertions
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 722febf13..dfdeabbdb 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -548,6 +548,7 @@ task_func_decl: AstNode *outreg = new AstNode(AST_WIRE); outreg->str = *$6; outreg->is_signed = $4; + outreg->is_reg = true; if ($5 != NULL) { outreg->children.push_back($5); outreg->is_signed = $4 || $5->is_signed; |