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verilog
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Author
Age
Files
Lines
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Add defaultvalue attribute
Clifford Wolf
2019-06-19
1
-0
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+11
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Fix handling of "logic" variables with initial value
Clifford Wolf
2019-06-19
1
-2
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+2
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Fixed brojen $error()/$info/$warning() on non-generate blocks
Udi Finkelstein
2019-06-11
2
-3
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+13
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Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...
Clifford Wolf
2019-06-07
2
-1
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+15
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Initial implementation of elaboration system tasks
Udi Finkelstein
2019-05-03
2
-1
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+15
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Cleanup tux3-implicit_named_connection
Clifford Wolf
2019-06-07
1
-1
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+1
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Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...
Clifford Wolf
2019-06-07
1
-1
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+10
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SystemVerilog support for implicit named port connections
tux3
2019-06-06
1
-9
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+17
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Fixed memory leak.
Maciej Kurc
2019-06-05
1
-0
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+4
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Added support for parsing attributes on port connections.
Maciej Kurc
2019-05-31
1
-10
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+10
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Merge branch 'master' into wandwor
Stefan Biereigel
2019-05-27
2
-9
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+19
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Added support for unsized constants, fixes #1022
Miodrag Milanovic
2019-05-27
2
-9
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+19
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fix indentation across files
Stefan Biereigel
2019-05-23
1
-2
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+2
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make lexer/parser aware of wand/wor net types
Stefan Biereigel
2019-05-23
2
-1
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+9
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Read bigger Verilog files.
Kaj Tuomi
2019-05-18
1
-1
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+1
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Merge pull request #1013 from antmicro/parameter_attributes
Clifford Wolf
2019-05-16
1
-2
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+2
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Added support for parsing attributes on parameters in Verilog frontent. Conte...
Maciej Kurc
2019-05-16
1
-2
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+2
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Make the generated *.tab.hh include all the headers needed to define the union.
Henner Zeller
2019-05-14
1
-1
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+9
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Merge pull request #946 from YosysHQ/clifford/specify
Clifford Wolf
2019-05-06
4
-33
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+328
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
Clifford Wolf
2019-05-06
2
-2
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+10
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Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung
2019-05-03
1
-2
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+2
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Improve $specrule interface
Clifford Wolf
2019-04-23
2
-9
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+19
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Improve $specrule interface
Clifford Wolf
2019-04-23
1
-20
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+18
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Add $specrule cells for $setup/$hold/$skew specify rules
Clifford Wolf
2019-04-23
2
-2
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+78
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Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...
Clifford Wolf
2019-04-23
1
-2
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+2
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Un-break default specify parser
Clifford Wolf
2019-04-23
1
-0
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+1
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Add specify parser
Clifford Wolf
2019-04-23
4
-33
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+243
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verilog_parser: Fix Bison warning
Ben Widawsky
2019-05-05
1
-1
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+1
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Merge pull request #988 from YosysHQ/clifford/fix987
Clifford Wolf
2019-05-04
2
-1
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+5
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Add approximate support for SV "var" keyword, fixes #987
Clifford Wolf
2019-05-04
2
-1
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+5
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Add support for SVA "final" keyword
Clifford Wolf
2019-05-04
2
-1
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+5
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Include filename in "Executing Verilog-2005 frontend" message, fixes #959
Clifford Wolf
2019-04-30
1
-2
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+2
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New behavior for front-end handling of whiteboxes
Clifford Wolf
2019-04-20
3
-16
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+30
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Add "whitebox" attribute, add "read_verilog -wb"
Clifford Wolf
2019-04-18
3
-7
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+20
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Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Clifford Wolf
2019-03-29
1
-0
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+2
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Improve read_verilog debug output capabilities
Clifford Wolf
2019-03-21
1
-5
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+24
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Fix handling of cases that look like sva labels, fixes #862
Clifford Wolf
2019-03-10
2
-92
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+66
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Also add support for labels on sva module items, fixes #699
Clifford Wolf
2019-03-08
2
-44
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+113
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Add support for SVA labels in read_verilog
Clifford Wolf
2019-03-07
1
-23
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+79
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Bugfix in Verilog string handling
Clifford Wolf
2019-01-05
1
-1
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+1
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Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-3
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+3
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verilog_parser: Properly handle recursion when processing attributes
Sylvain Munaut
2018-12-14
1
-19
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+29
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Add warning for SV "restrict" without "property"
Clifford Wolf
2018-11-04
1
-2
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+11
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Fix minor typo in error message
Clifford Wolf
2018-10-25
1
-1
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+1
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Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...
Udi Finkelstein
2018-10-25
1
-14
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+14
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Merge pull request #659 from rubund/sv_interfaces
Clifford Wolf
2018-10-18
2
-0
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+88
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Handle FIXME for modport members without type directly in front
Ruben Undheim
2018-10-13
1
-6
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+8
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Support for 'modports' for System Verilog interfaces
Ruben Undheim
2018-10-12
1
-3
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+21
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Synthesis support for SystemVerilog interfaces
Ruben Undheim
2018-10-12
2
-0
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+68
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ignore protect endprotect
argama
2018-10-16
1
-0
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+3
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