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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 15:05:57 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 15:05:57 -0700 |
| commit | d9c4644e88b916d1eadfd401abf297c0995b6462 (patch) | |
| tree | c6355f3671d0399814f5e9257e7f5decdf906b7f /frontends/verilog | |
| parent | 67005633e246e47683b11e13f08afb788bc9de02 (diff) | |
| parent | c2e29ab809c5eb3ac89d50868d0e88d831c33d52 (diff) | |
| download | yosys-d9c4644e88b916d1eadfd401abf297c0995b6462.tar.gz yosys-d9c4644e88b916d1eadfd401abf297c0995b6462.tar.bz2 yosys-d9c4644e88b916d1eadfd401abf297c0995b6462.zip | |
Merge remote-tracking branch 'origin/master' into clifford/specify
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_frontend.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 8202ab9d7..01e589efb 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -246,8 +246,6 @@ struct VerilogFrontend : public Frontend { specify_mode = false; default_nettype_wire = true; - log_header(design, "Executing Verilog-2005 frontend.\n"); - args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); size_t argidx; @@ -423,6 +421,8 @@ struct VerilogFrontend : public Frontend { } extra_args(f, filename, args, argidx); + log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str()); + log("Parsing %s%s input from `%s' to AST representation.\n", formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); |