index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
frontends
/
verilog
Commit message (
Expand
)
Author
Age
Files
Lines
...
*
|
Fixed brojen $error()/$info/$warning() on non-generate blocks
Udi Finkelstein
2019-06-11
2
-3
/
+13
|
/
*
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...
Clifford Wolf
2019-06-07
2
-1
/
+15
|
\
|
*
Initial implementation of elaboration system tasks
Udi Finkelstein
2019-05-03
2
-1
/
+15
*
|
Cleanup tux3-implicit_named_connection
Clifford Wolf
2019-06-07
1
-1
/
+1
*
|
Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...
Clifford Wolf
2019-06-07
1
-1
/
+10
|
\
\
|
*
|
SystemVerilog support for implicit named port connections
tux3
2019-06-06
1
-9
/
+17
*
|
|
Fixed memory leak.
Maciej Kurc
2019-06-05
1
-0
/
+4
*
|
|
Added support for parsing attributes on port connections.
Maciej Kurc
2019-05-31
1
-10
/
+10
|
/
/
*
|
Merge branch 'master' into wandwor
Stefan Biereigel
2019-05-27
2
-9
/
+19
|
\
\
|
*
|
Added support for unsized constants, fixes #1022
Miodrag Milanovic
2019-05-27
2
-9
/
+19
*
|
|
fix indentation across files
Stefan Biereigel
2019-05-23
1
-2
/
+2
*
|
|
make lexer/parser aware of wand/wor net types
Stefan Biereigel
2019-05-23
2
-1
/
+9
|
/
/
*
|
Read bigger Verilog files.
Kaj Tuomi
2019-05-18
1
-1
/
+1
*
|
Merge pull request #1013 from antmicro/parameter_attributes
Clifford Wolf
2019-05-16
1
-2
/
+2
|
\
\
|
*
|
Added support for parsing attributes on parameters in Verilog frontent. Conte...
Maciej Kurc
2019-05-16
1
-2
/
+2
*
|
|
Make the generated *.tab.hh include all the headers needed to define the union.
Henner Zeller
2019-05-14
1
-1
/
+9
|
/
/
*
|
Merge pull request #946 from YosysHQ/clifford/specify
Clifford Wolf
2019-05-06
4
-33
/
+328
|
\
\
|
*
\
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify
Clifford Wolf
2019-05-06
2
-2
/
+10
|
|
\
\
|
*
\
\
Merge remote-tracking branch 'origin/master' into clifford/specify
Eddie Hung
2019-05-03
1
-2
/
+2
|
|
\
\
\
|
|
|
|
/
|
|
|
/
|
|
*
|
|
Improve $specrule interface
Clifford Wolf
2019-04-23
2
-9
/
+19
|
*
|
|
Improve $specrule interface
Clifford Wolf
2019-04-23
1
-20
/
+18
|
*
|
|
Add $specrule cells for $setup/$hold/$skew specify rules
Clifford Wolf
2019-04-23
2
-2
/
+78
|
*
|
|
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...
Clifford Wolf
2019-04-23
1
-2
/
+2
|
*
|
|
Un-break default specify parser
Clifford Wolf
2019-04-23
1
-0
/
+1
|
*
|
|
Add specify parser
Clifford Wolf
2019-04-23
4
-33
/
+243
*
|
|
|
verilog_parser: Fix Bison warning
Ben Widawsky
2019-05-05
1
-1
/
+1
|
|
_
|
/
|
/
|
|
*
|
|
Merge pull request #988 from YosysHQ/clifford/fix987
Clifford Wolf
2019-05-04
2
-1
/
+5
|
\
\
\
|
*
|
|
Add approximate support for SV "var" keyword, fixes #987
Clifford Wolf
2019-05-04
2
-1
/
+5
|
|
|
/
|
|
/
|
*
/
|
Add support for SVA "final" keyword
Clifford Wolf
2019-05-04
2
-1
/
+5
|
/
/
*
/
Include filename in "Executing Verilog-2005 frontend" message, fixes #959
Clifford Wolf
2019-04-30
1
-2
/
+2
|
/
*
New behavior for front-end handling of whiteboxes
Clifford Wolf
2019-04-20
3
-16
/
+30
*
Add "whitebox" attribute, add "read_verilog -wb"
Clifford Wolf
2019-04-18
3
-7
/
+20
*
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Clifford Wolf
2019-03-29
1
-0
/
+2
*
Improve read_verilog debug output capabilities
Clifford Wolf
2019-03-21
1
-5
/
+24
*
Fix handling of cases that look like sva labels, fixes #862
Clifford Wolf
2019-03-10
2
-92
/
+66
*
Also add support for labels on sva module items, fixes #699
Clifford Wolf
2019-03-08
2
-44
/
+113
*
Add support for SVA labels in read_verilog
Clifford Wolf
2019-03-07
1
-23
/
+79
*
Bugfix in Verilog string handling
Clifford Wolf
2019-01-05
1
-1
/
+1
*
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-3
/
+3
*
verilog_parser: Properly handle recursion when processing attributes
Sylvain Munaut
2018-12-14
1
-19
/
+29
*
Add warning for SV "restrict" without "property"
Clifford Wolf
2018-11-04
1
-2
/
+11
*
Fix minor typo in error message
Clifford Wolf
2018-10-25
1
-1
/
+1
*
Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...
Udi Finkelstein
2018-10-25
1
-14
/
+14
*
Merge pull request #659 from rubund/sv_interfaces
Clifford Wolf
2018-10-18
2
-0
/
+88
|
\
|
*
Handle FIXME for modport members without type directly in front
Ruben Undheim
2018-10-13
1
-6
/
+8
|
*
Support for 'modports' for System Verilog interfaces
Ruben Undheim
2018-10-12
1
-3
/
+21
|
*
Synthesis support for SystemVerilog interfaces
Ruben Undheim
2018-10-12
2
-0
/
+68
*
|
ignore protect endprotect
argama
2018-10-16
1
-0
/
+3
|
/
*
Add "read_verilog -noassert -noassume -assert-assumes"
Clifford Wolf
2018-09-24
3
-6
/
+49
*
Added support for ommited "parameter" in Verilog-2001 style parameter decl in...
Clifford Wolf
2018-09-23
1
-3
/
+9
[prev]
[next]