| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fix partsel expr bit width handling and add test case | Claire Wolf | 2020-03-08 | 1 | -4/+6 |
| * | Fix bison warning for "pure-parser" option | Claire Wolf | 2020-03-03 | 1 | -1/+1 |
| * | Closes #1717. Add more precise Verilog source location information to AST and... | Alberto Gonzalez | 2020-02-23 | 4 | -32/+131 |
| * | Merge pull request #1703 from YosysHQ/eddie/specify_improve | Eddie Hung | 2020-02-21 | 2 | -29/+81 |
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| | * | verilog: add support for more delays than just rise/fall | Eddie Hung | 2020-02-19 | 1 | -1/+40 |
| | * | verilog: ignore ranges too without -specify | Eddie Hung | 2020-02-13 | 1 | -1/+2 |
| | * | verilog: improve specify support when not in -specify mode | Eddie Hung | 2020-02-13 | 1 | -13/+7 |
| | * | verilog: ignore '&&&' when not in -specify mode | Eddie Hung | 2020-02-13 | 2 | -5/+6 |
| | * | specify: system timing checks to accept min:typ:max triple | Eddie Hung | 2020-02-13 | 1 | -12/+29 |
| * | | Merge pull request #1642 from jjj11x/jjj11x/sv-enum | Claire Wolf | 2020-02-20 | 1 | -2/+104 |
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| | * | add attributes for enumerated values in ilang | Jeff Wang | 2020-02-17 | 1 | -1/+8 |
| | * | lexer doesn't seem to return TOK_REG for logic anymore | Jeff Wang | 2020-01-16 | 1 | -3/+4 |
| | * | allow enum typedefs | Jeff Wang | 2020-01-16 | 1 | -1/+6 |
| | * | partial rebase of PeterCrozier's enum work onto current master | Jeff Wang | 2020-01-16 | 1 | -1/+90 |
| * | | Merge pull request #1679 from thasti/delay-parsing | N. Engelhardt | 2020-02-13 | 1 | -2/+2 |
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| | * | | correct wire declaration grammar for #1614 | Stefan Biereigel | 2020-02-03 | 1 | -2/+2 |
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| * | | sv: Improve handling of wildcard port connections | David Shah | 2020-02-02 | 2 | -4/+6 |
| * | | hierarchy: Resolve SV wildcard port connections | David Shah | 2020-02-02 | 1 | -1/+1 |
| * | | sv: Add lexing and parsing of .* (wildcard port conns) | David Shah | 2020-02-02 | 2 | -1/+6 |
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| * | Fixed some missing "verilog_" in documentation | Rodrigo Alejandro Melo | 2019-12-13 | 2 | -2/+2 |
| * | kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr. | whitequark | 2019-12-04 | 1 | -5/+5 |
| * | sv: Correct parsing of always_comb, always_ff and always_latch | David Shah | 2019-11-21 | 2 | -5/+40 |
| * | Add check for valid macro names in macro definitions | Clifford Wolf | 2019-11-07 | 1 | -7/+11 |
| * | Add "verilog_defines -list" and "verilog_defines -reset" | Clifford Wolf | 2019-10-21 | 1 | -0/+16 |
| * | Use "(id)" instead of "id" for types as temporary hack | Clifford Wolf | 2019-10-14 | 1 | -11/+69 |
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| | * | sv: Disambiguate interface ports | David Shah | 2019-10-03 | 1 | -3/+19 |
| | * | sv: Fix memories of typedefs | David Shah | 2019-10-03 | 1 | -1/+1 |
| | * | sv: Add %expect | David Shah | 2019-10-03 | 1 | -0/+1 |
| | * | sv: Add support for memory typedefs | David Shah | 2019-10-03 | 1 | -1/+19 |
| | * | sv: Fix typedef parameters | David Shah | 2019-10-03 | 1 | -4/+17 |
| | * | sv: Switch parser to glr, prep for typedef | David Shah | 2019-10-03 | 1 | -4/+34 |
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| * | Fix handling of z_digit "?" and fix optimization of cmp with "z" | Clifford Wolf | 2019-09-13 | 1 | -5/+1 |
| * | Fix lexing of integer literals without radix | Clifford Wolf | 2019-09-13 | 1 | -1/+1 |
| * | Fix lexing of integer literals, fixes #1364 | Clifford Wolf | 2019-09-12 | 2 | -3/+3 |
| * | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -4/+4 |
| * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -12/+12 |
| * | verilog_lexer: Increase YY_BUF_SIZE to 65536 | David Shah | 2019-07-26 | 1 | -0/+3 |
| * | Merge pull request #1147 from YosysHQ/clifford/fix1144 | Clifford Wolf | 2019-07-03 | 1 | -81/+14 |
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| | * | Some cleanups in "ignore specify parser" | Clifford Wolf | 2019-07-03 | 1 | -79/+5 |
| | * | Improve specify dummy parser, fixes #1144 | Clifford Wolf | 2019-06-28 | 1 | -2/+9 |
| * | | Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/Symbi... | Clifford Wolf | 2019-07-02 | 1 | -0/+2 |
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| * | Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 | Clifford Wolf | 2019-06-26 | 1 | -1/+1 |
| * | Merge pull request #1119 from YosysHQ/eddie/fix1118 | Clifford Wolf | 2019-06-21 | 1 | -0/+1 |
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| | * | Make genvar a signed type | Eddie Hung | 2019-06-20 | 1 | -0/+1 |
| * | | Maintain "is_unsized" state of constants | Eddie Hung | 2019-06-20 | 1 | -6/+6 |
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| * | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo... | Clifford Wolf | 2019-06-20 | 1 | -1/+7 |
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| | * | Unpacked array declaration using size | Tobias Wölfel | 2019-06-19 | 1 | -1/+7 |
| * | | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 2 | -3/+15 |
| * | | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 1 | -0/+11 |
| * | | Fix handling of "logic" variables with initial value | Clifford Wolf | 2019-06-19 | 1 | -2/+2 |
