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| author | David Shah <dave@ds0.me> | 2019-11-22 15:07:55 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2020-02-02 16:12:33 +0000 |
| commit | 4bfd2ef4f328b4a95918ed3e0d7a7e38406c4ae8 (patch) | |
| tree | 9c5e0ed53f701187915b10a4b9256fadfc88537e /frontends/verilog | |
| parent | ebe1d7d5ab798b945bf2aa0e818ffe7152995071 (diff) | |
| download | yosys-4bfd2ef4f328b4a95918ed3e0d7a7e38406c4ae8.tar.gz yosys-4bfd2ef4f328b4a95918ed3e0d7a7e38406c4ae8.tar.bz2 yosys-4bfd2ef4f328b4a95918ed3e0d7a7e38406c4ae8.zip | |
sv: Improve handling of wildcard port connections
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 | ||||
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 8 |
2 files changed, 6 insertions, 4 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 39520bd51..9b43c250e 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -431,7 +431,7 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ { "+:" { return TOK_POS_INDEXED; } "-:" { return TOK_NEG_INDEXED; } -".*" { return TOK_AUTOCONNECT_ALL; } +".*" { return TOK_WILDCARD_CONNECT; } [-+]?[=*]> { if (!specify_mode) REJECT; diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 5ec8e66a6..2c7304cc4 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -138,7 +138,7 @@ struct specify_rise_fall { %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP -%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_AUTOCONNECT_ALL +%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH @@ -1581,8 +1581,10 @@ cell_port: delete $3; free_attr($1); } | - attr TOK_AUTOCONNECT_ALL { - astbuf2->attributes[ID(implicit_port_conns)] = AstNode::mkconst_int(1, false); + attr TOK_WILDCARD_CONNECT { + if (!sv_mode) + frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode."); + astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false); }; always_comb_or_latch: |