iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Updated .gitignore file for ilang and verilog frontends	Clifford Wolf	2014-10-15	1	-4/+4
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*	Replaced readsome() with read() and gcount()	Clifford Wolf	2014-10-15	1	-3/+5
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*	Updated lexers & parsers to include prefixes	William Speirs	2014-10-15	3	-14/+18
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*	Fixed win32 troubles with f.readsome()	Clifford Wolf	2014-10-11	2	-2/+2
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*	Added format __attribute__ to stringf()	Clifford Wolf	2014-10-10	1	-1/+1
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-16/+16
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*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23	1	-4/+1
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	5	-22/+30
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*	Added support for non-standard <plugin>:<c_name> DPI syntax	Clifford Wolf	2014-08-22	1	-0/+12
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*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21	2	-5/+16
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*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21	2	-1/+54
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*	Added support for global tasks and functions	Clifford Wolf	2014-08-21	2	-15/+23
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*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18	1	-12/+14
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*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14	1	-4/+9
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*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13	1	-1/+12
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*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07	1	-3/+5
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*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	1	-4/+18
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	1	-2/+1
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*	Added support for non-standard "module mod_name(...);" syntax	Clifford Wolf	2014-08-04	1	-1/+7
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	6	-3/+24
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*	Fixed counting verilog line numbers for "// synopsys translate_off" sections	Clifford Wolf	2014-07-30	2	-4/+4
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*	Fixed Verilog pre-processor for files with no trailing newline	Clifford Wolf	2014-07-29	1	-1/+1
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	3	-5/+2
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-3/+3
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*	fixed parsing of constant with comment between size and value	Clifford Wolf	2014-07-02	1	-0/+7
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*	Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)	Clifford Wolf	2014-06-16	1	-5/+11
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*	Improved parsing of large integer constants	Clifford Wolf	2014-06-15	1	-11/+28
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*	Added handling of real-valued parameters/localparams	Clifford Wolf	2014-06-14	2	-7/+15
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*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	2	-3/+24
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*	Added read_verilog -sv options, added support for bit, logic,	Clifford Wolf	2014-06-12	4	-3/+37
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*	Add support for cell arrays	Clifford Wolf	2014-06-07	1	-0/+7
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*	made the generate..endgenrate keywords optional	Clifford Wolf	2014-06-06	1	-4/+8
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*	added while and repeat support to verilog parser	Clifford Wolf	2014-06-06	2	-1/+29
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*	Improved error message for options after front-end filename arguments	Clifford Wolf	2014-06-04	1	-1/+1
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*	Fixed clang -Wdeprecated-register warnings	Clifford Wolf	2014-04-20	1	-0/+5
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*	Replaced depricated %name-prefix= bison directive	Clifford Wolf	2014-04-20	1	-1/+1
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	1	-0/+1
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*	Added support for `line compiler directive	Clifford Wolf	2014-03-11	1	-0/+11
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*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	5	-2/+18
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*	Added a warning note about error reporting to read_verilog help message	Clifford Wolf	2014-02-16	1	-0/+5
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	1	-1/+11
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*	Added support for functions returning integer	Clifford Wolf	2014-02-12	1	-2/+12
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*	Added read_verilog -setattr	Clifford Wolf	2014-02-05	1	-0/+15
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*	Added support for blanks after -I and -D in read_verilog	Clifford Wolf	2014-02-02	1	-7/+20
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*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	1	-0/+22
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*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	1	-1/+9
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*	Fixed handling of unsized constants in verilog frontend	Clifford Wolf	2014-01-24	1	-2/+2
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*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	2	-3/+10
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*	Fixed parsing of verilog macros at end of line	Clifford Wolf	2014-01-18	1	-1/+1
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