aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/verilog
Commit message (Expand)AuthorAgeFilesLines
* Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...Clifford Wolf2019-06-072-1/+15
|\
| * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-1/+15
* | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-1/+1
* | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-071-1/+10
|\ \
| * | SystemVerilog support for implicit named port connectionstux32019-06-061-9/+17
* | | Fixed memory leak.Maciej Kurc2019-06-051-0/+4
* | | Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
|/ /
* | Merge branch 'master' into wandworStefan Biereigel2019-05-272-9/+19
|\ \
| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-272-9/+19
* | | fix indentation across filesStefan Biereigel2019-05-231-2/+2
* | | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-232-1/+9
|/ /
* | Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
* | Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
|\ \
| * | Added support for parsing attributes on parameters in Verilog frontent. Conte...Maciej Kurc2019-05-161-2/+2
* | | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-141-1/+9
|/ /
* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-064-33/+328
|\ \
| * \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-062-2/+10
| |\ \
| * \ \ Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-2/+2
| |\ \ \ | | | |/ | | |/|
| * | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-232-2/+78
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-2/+2
| * | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| * | | Add specify parserClifford Wolf2019-04-234-33/+243
* | | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
| |_|/ |/| |
* | | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
|\ \ \
| * | | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
| | |/ | |/|
* / | Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
|/ /
* / Include filename in "Executing Verilog-2005 frontend" message, fixes #959Clifford Wolf2019-04-301-2/+2
|/
* New behavior for front-end handling of whiteboxesClifford Wolf2019-04-203-16/+30
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-183-7/+20
* Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906Clifford Wolf2019-03-291-0/+2
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-211-5/+24
* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-102-92/+66
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-082-44/+113
* Add support for SVA labels in read_verilogClifford Wolf2019-03-071-23/+79
* Bugfix in Verilog string handlingClifford Wolf2019-01-051-1/+1
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
* Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-251-14/+14
* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-182-0/+88
|\
| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+21
| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-122-0/+68
* | ignore protect endprotectargama2018-10-161-0/+3
|/
* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
* Added support for ommited "parameter" in Verilog-2001 style parameter decl in...Clifford Wolf2018-09-231-3/+9
* Add "make coverage"Clifford Wolf2018-08-273-6/+5
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 04:45:21 +0000