aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/verilog
Commit message (Expand)AuthorAgeFilesLines
* verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
* verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-2/+0
* verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
* verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
* Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-11/+9
|\
| * Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| * verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
* | verilog: default to input in sv mode if task/func has no dir ...Eddie Hung2020-05-131-2/+10
* | verilog: error out when non-ANSI task/func argumentsEddie Hung2020-05-111-1/+5
|/
* Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-2/+2
|\
| * Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-2/+2
* | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-061-1/+6
|\ \
| * | verilog: allow null gen-if then blockZachary Snow2020-05-061-1/+6
| |/
* | Merge pull request #2025 from YosysHQ/eddie/frontend_cleanupEddie Hung2020-05-053-15/+15
|\ \
| * | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-043-15/+15
| |/
* | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-1/+3
|\ \
| * | verilog: set src attribute for primitivesEddie Hung2020-05-041-1/+3
| |/
* / verilog: fix specify src attributeEddie Hung2020-05-041-18/+20
|/
* Set Verilog source location for explicit blocks (`begin` ... `end`).Alberto Gonzalez2020-04-171-0/+1
* Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` no...Alberto Gonzalez2020-04-171-0/+2
* Add location information to `AST_CONSTANT` nodes.Alberto Gonzalez2020-04-161-0/+3
* Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-1/+2
|\
| * support using previously declared types/localparams/params in packageJeff Wang2020-04-071-1/+2
* | verilog: Fix write to deleted objectDavid Shah2020-04-121-1/+0
|/
* Merge pull request #1767 from YosysHQ/eddie/idstringsEddie Hung2020-04-021-27/+27
|\
| * kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-5/+5
| * kernel: use more ID::*Eddie Hung2020-04-021-22/+22
* | Merge pull request #1846 from dh73/ast_feClaire Wolf2020-04-021-0/+3
|\ \ | |/ |/|
| * Replacing log_error for log_file_error due consistencyDiego H2020-03-311-2/+1
| * Adding error message for when size (width) of number literal is zeroDiego H2020-03-301-0/+4
* | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
|/
* Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-304-41/+81
|\
| * Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
| * Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-242-3/+11
| * Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-234-20/+56
* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-149/+578
|/
* Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
* Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
* Parser changes to support typedef.Peter2020-03-224-10/+88
* Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
|\
| * Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
* | Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-191-7/+30
|\ \ | |/ |/|
| * Add precise locations for assertshuaixv2020-03-191-7/+30
* | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
|/
* Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-19/+43
|\
| * refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-112-19/+43
* | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
* | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
|/
* Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
* Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-03 15:10:16 +0000