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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-17 06:23:03 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-17 06:23:03 +0000 |
| commit | 00d74f0b9ceecc7b60f50fddb3b6ab0c47701923 (patch) | |
| tree | 1689f29481eb5ac889427035b71b2bdc05aa4782 /frontends/verilog | |
| parent | 10a814f97808de8cce7e50a03f01832db66c263e (diff) | |
| download | yosys-00d74f0b9ceecc7b60f50fddb3b6ab0c47701923.tar.gz yosys-00d74f0b9ceecc7b60f50fddb3b6ab0c47701923.tar.bz2 yosys-00d74f0b9ceecc7b60f50fddb3b6ab0c47701923.zip | |
Set Verilog source location for explicit blocks (`begin` ... `end`).
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index f762f9025..4a5aba79e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2246,6 +2246,7 @@ behavioral_stmt: exitTypeScope(); if ($4 != NULL && $8 != NULL && *$4 != *$8) frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1); + SET_AST_NODE_LOC(ast_stack.back(), @2, @8); delete $4; delete $8; ast_stack.pop_back(); |