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| author | Zachary Snow <zach@zachjs.com> | 2021-02-06 23:54:17 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-02-07 11:48:39 -0500 |
| commit | 1d5f3fe5064146955dafdabafe7180ff79c95d08 (patch) | |
| tree | ccc9c6a40e9ea885b693f6c2e51202f4217453d2 /frontends/verilog/verilog_parser.y | |
| parent | eff18a2b1519428b11400979f116342086c13e13 (diff) | |
| download | yosys-1d5f3fe5064146955dafdabafe7180ff79c95d08.tar.gz yosys-1d5f3fe5064146955dafdabafe7180ff79c95d08.tar.bz2 yosys-1d5f3fe5064146955dafdabafe7180ff79c95d08.zip | |
verlog: allow shadowing module ports within generate blocks
This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index fb5846f7b..0aae25353 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1784,7 +1784,13 @@ wire_name: } rewriteAsMemoryNode(node, $2); } - if (current_function_or_task == NULL) { + if (current_function_or_task) { + if (node->is_input || node->is_output) + node->port_id = current_function_or_task_port_id++; + } else if (ast_stack.back()->type == AST_GENBLOCK) { + if (node->is_input || node->is_output) + frontend_verilog_yyerror("Cannot declare module port `%s' within a generate block.", $1->c_str()); + } else { if (do_not_require_port_stubs && (node->is_input || node->is_output) && port_stubs.count(*$1) == 0) { port_stubs[*$1] = ++port_counter; } @@ -1799,9 +1805,6 @@ wire_name: if (node->is_input || node->is_output) frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str()); } - } else { - if (node->is_input || node->is_output) - node->port_id = current_function_or_task_port_id++; } //FIXME: for some reason, TOK_ID has a location which always points to one column *after* the real last column... SET_AST_NODE_LOC(node, @1, @1); |