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* Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-101-43/+56
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-081-39/+61
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA labels in read_verilogClifford Wolf2019-03-071-23/+79
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-3/+3
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
| | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-251-14/+14
| | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
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* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+21
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* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+60
| | | | This time doing the changes mostly in AST before RTLIL generation
* Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-241-5/+18
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-09-231-3/+9
| | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
* Yosys can now parse ↵Udi Finkelstein2018-08-201-10/+22
| | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value.
* A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| | | | Just remember specify blocks are parsed but ignored.
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-151-1/+6
|\ | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
| * Modified errors into warningsUdi Finkelstein2018-06-051-0/+1
| | | | | | | | No longer false warnings for memories and assertions
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
* | Detect illegal port declaration, e.g input/output/inout keyword must be the ↵Udi Finkelstein2018-06-061-3/+6
| | | | | | | | first.
* | Add statement labels for immediate assertionsClifford Wolf2018-04-131-18/+21
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Allow "property" in immediate assertionsClifford Wolf2018-04-121-17/+20
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add read_verilog anyseq/anyconst/allseq/allconst attribute supportClifford Wolf2018-04-061-1/+33
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-2/+167
|/ | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Verilog "automatic" keyword (ignored in synthesis)Clifford Wolf2017-11-231-13/+17
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* Accept real-valued delay valuesClifford Wolf2017-11-181-0/+1
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* Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵Udi Finkelstein2017-09-301-3/+5
| | | | | | textbook solution (Oreilly 'Flex & Bison' page 189)
* Fix ignoring of simulation timings so that invalid module parameters cause ↵Clifford Wolf2017-09-261-0/+2
| | | | syntax errors
* Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand ↵Clifford Wolf2017-06-071-0/+1
| | | | const reg"
* Fix handling of Verilog ~& and ~| operatorsClifford Wolf2017-06-011-0/+8
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* Add support for localparam in module headerClifford Wolf2017-04-301-1/+7
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* Allow $anyconst, etc. in non-formal SV modeClifford Wolf2017-03-011-1/+1
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* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-1/+25
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* Add support for SystemVerilog unique, unique0, and priority caseClifford Wolf2017-02-231-4/+21
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* Added SystemVerilog support for ++ and --Clifford Wolf2017-02-231-0/+9
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* Add checker support to verilog front-endClifford Wolf2017-02-091-2/+13
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* Add SV "rand" and "const rand" supportClifford Wolf2017-02-081-6/+24
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* Further improve cover() supportClifford Wolf2017-02-041-0/+6
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* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-1/+7
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* Add "enum" and "typedef" lexer supportClifford Wolf2017-01-171-1/+1
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* Added support for hierarchical defparamsClifford Wolf2016-11-151-3/+2
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* Added $anyseq cell typeClifford Wolf2016-10-141-1/+1
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* Removed $aconst cell typeClifford Wolf2016-08-301-1/+1
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* Removed $predict againClifford Wolf2016-08-281-7/+1
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* Added read_verilog -norestrict -assume-assertsClifford Wolf2016-08-261-3/+16
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* Improved verilog parser errorsClifford Wolf2016-08-251-0/+3
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* Fixed bug in parsing real constantsClifford Wolf2016-08-061-4/+4
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* Added $anyconst and $aconstClifford Wolf2016-07-271-1/+1
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* Fixed a verilog parser memory leakClifford Wolf2016-07-251-0/+1
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