index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
frontends
/
verilog
/
verilog_parser.y
Commit message (
Expand
)
Author
Age
Files
Lines
*
Fix handling of cases that look like sva labels, fixes #862
Clifford Wolf
2019-03-10
1
-43
/
+56
*
Also add support for labels on sva module items, fixes #699
Clifford Wolf
2019-03-08
1
-39
/
+61
*
Add support for SVA labels in read_verilog
Clifford Wolf
2019-03-07
1
-23
/
+79
*
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
1
-3
/
+3
*
verilog_parser: Properly handle recursion when processing attributes
Sylvain Munaut
2018-12-14
1
-19
/
+29
*
Add warning for SV "restrict" without "property"
Clifford Wolf
2018-11-04
1
-2
/
+11
*
Fix minor typo in error message
Clifford Wolf
2018-10-25
1
-1
/
+1
*
Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...
Udi Finkelstein
2018-10-25
1
-14
/
+14
*
Handle FIXME for modport members without type directly in front
Ruben Undheim
2018-10-13
1
-6
/
+8
*
Support for 'modports' for System Verilog interfaces
Ruben Undheim
2018-10-12
1
-3
/
+21
*
Synthesis support for SystemVerilog interfaces
Ruben Undheim
2018-10-12
1
-0
/
+60
*
Add "read_verilog -noassert -noassume -assert-assumes"
Clifford Wolf
2018-09-24
1
-5
/
+18
*
Added support for ommited "parameter" in Verilog-2001 style parameter decl in...
Clifford Wolf
2018-09-23
1
-3
/
+9
*
Fixed all known specify/endspecify issues, without breaking 'make test'.
Udi Finkelstein
2018-08-20
1
-12
/
+12
*
Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-rout...
Udi Finkelstein
2018-08-20
1
-10
/
+22
*
A few minor enhancements to specify block parsing.
Udi Finkelstein
2018-08-15
1
-2
/
+13
*
Merge pull request #513 from udif/pr_reg_wire_error
Clifford Wolf
2018-08-15
1
-1
/
+6
|
\
|
*
Modified errors into warnings
Udi Finkelstein
2018-06-05
1
-0
/
+1
|
*
This PR should be the base for discussion, do not merge it yet!
Udi Finkelstein
2018-03-11
1
-1
/
+5
*
|
Detect illegal port declaration, e.g input/output/inout keyword must be the f...
Udi Finkelstein
2018-06-06
1
-3
/
+6
*
|
Add statement labels for immediate assertions
Clifford Wolf
2018-04-13
1
-18
/
+21
*
|
Allow "property" in immediate assertions
Clifford Wolf
2018-04-12
1
-17
/
+20
*
|
Add read_verilog anyseq/anyconst/allseq/allconst attribute support
Clifford Wolf
2018-04-06
1
-1
/
+33
*
|
First draft of Verilog parser support for specify blocks and parameters.
Udi Finkelstein
2018-03-27
1
-2
/
+167
|
/
*
Add $allconst and $allseq cell types
Clifford Wolf
2018-02-23
1
-1
/
+3
*
Add Verilog "automatic" keyword (ignored in synthesis)
Clifford Wolf
2017-11-23
1
-13
/
+17
*
Accept real-valued delay values
Clifford Wolf
2017-11-18
1
-0
/
+1
*
Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textboo...
Udi Finkelstein
2017-09-30
1
-3
/
+5
*
Fix ignoring of simulation timings so that invalid module parameters cause sy...
Clifford Wolf
2017-09-26
1
-0
/
+2
*
Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons...
Clifford Wolf
2017-06-07
1
-0
/
+1
*
Fix handling of Verilog ~& and ~| operators
Clifford Wolf
2017-06-01
1
-0
/
+8
*
Add support for localparam in module header
Clifford Wolf
2017-04-30
1
-1
/
+7
*
Allow $anyconst, etc. in non-formal SV mode
Clifford Wolf
2017-03-01
1
-1
/
+1
*
Add $live and $fair cell types, add support for s_eventually keyword
Clifford Wolf
2017-02-25
1
-1
/
+25
*
Add support for SystemVerilog unique, unique0, and priority case
Clifford Wolf
2017-02-23
1
-4
/
+21
*
Added SystemVerilog support for ++ and --
Clifford Wolf
2017-02-23
1
-0
/
+9
*
Add checker support to verilog front-end
Clifford Wolf
2017-02-09
1
-2
/
+13
*
Add SV "rand" and "const rand" support
Clifford Wolf
2017-02-08
1
-6
/
+24
*
Further improve cover() support
Clifford Wolf
2017-02-04
1
-0
/
+6
*
Add $cover cell type and SVA cover() support
Clifford Wolf
2017-02-04
1
-1
/
+7
*
Add "enum" and "typedef" lexer support
Clifford Wolf
2017-01-17
1
-1
/
+1
*
Added support for hierarchical defparams
Clifford Wolf
2016-11-15
1
-3
/
+2
*
Added $anyseq cell type
Clifford Wolf
2016-10-14
1
-1
/
+1
*
Removed $aconst cell type
Clifford Wolf
2016-08-30
1
-1
/
+1
*
Removed $predict again
Clifford Wolf
2016-08-28
1
-7
/
+1
*
Added read_verilog -norestrict -assume-asserts
Clifford Wolf
2016-08-26
1
-3
/
+16
*
Improved verilog parser errors
Clifford Wolf
2016-08-25
1
-0
/
+3
*
Fixed bug in parsing real constants
Clifford Wolf
2016-08-06
1
-4
/
+4
*
Added $anyconst and $aconst
Clifford Wolf
2016-07-27
1
-1
/
+1
*
Fixed a verilog parser memory leak
Clifford Wolf
2016-07-25
1
-0
/
+1
[next]