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path: root/frontends/verilog/verilog_parser.y
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* verilog: Support void functionsJannis Harder2023-03-201-1/+18
* Resolve struct member package typesDag Lem2023-01-291-0/+7
* Correct interpretation of SystemVerilog C-style array dimensionsDag Lem2022-11-131-3/+3
* verilog: support for time scale delay valuesZachary Snow2022-02-141-1/+4
* Specify minimum bison version 3.0+Zachary Snow2021-10-011-0/+2
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-241-0/+1
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| * Fix TOK_ID memory leak in for_initializationZachary Snow2021-09-231-0/+1
* | sv: support wand and wor of data typesZachary Snow2021-09-211-9/+12
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-211-0/+1
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* sv: support declaration in generate for initializationZachary Snow2021-08-311-1/+95
* sv: support declaration in procedural for initializationZachary Snow2021-08-301-1/+48
* sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-121-11/+44
* Allow optional comma after last entry in enumMichael Singer2021-08-091-11/+12
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-161-3/+74
* sv: fix a few struct and enum memory leaksZachary Snow2021-07-061-2/+4
* sv: fix up end label checkingZachary Snow2021-06-161-7/+18
* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
* verilog: fix leaking ASTNodesXiretza2021-06-141-7/+10
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-141-9/+8
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* sv: support tasks and functions within packagesZachary Snow2021-06-011-1/+1
* sv: support remaining assignment operatorsZachary Snow2021-05-251-38/+30
* sv: check validity of package end labelZachary Snow2021-05-101-0/+2
* verilog: check entire user type stack for type definitionXiretza2021-03-211-6/+12
* sv: allow typenames as function return typesZachary Snow2021-03-191-0/+6
* sv: support for parameters without default valuesZachary Snow2021-03-021-3/+21
* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-011-2/+3
* sv: extended support for integer typesZachary Snow2021-02-281-39/+69
* Fix handling of unique/unique0/priority cases in the frontend.Marcelina Kościelnicka2021-02-251-14/+15
* Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and tu...TimRudy2021-02-241-2/+7
* Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-4/+7
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| * verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-4/+7
* | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-4/+4
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* Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+2
* verilog: significant block scoping improvementsZachary Snow2021-01-311-17/+28
* Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
* sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
* Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
* sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
* Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
* Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
* Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
* Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
* Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
* Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
* Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-101-10/+19
* Revert PRs #2203 and #2244.whitequark2020-07-091-19/+10
* Support logic typed parametersLukasz Dalek2020-07-061-7/+10
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