| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Also add support for labels on sva module items, fixes #699 | Clifford Wolf | 2019-03-08 | 1 | -5/+52 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Bugfix in Verilog string handling | Clifford Wolf | 2019-01-05 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 1 | -0/+8 | |
| |\ | | | | | Support for SystemVerilog interfaces and modports | |||||
| | * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+8 | |
| | | | | | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | | ignore protect endprotect | argama | 2018-10-16 | 1 | -0/+3 | |
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| * | Add "make coverage" | Clifford Wolf | 2018-08-27 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 1 | -1/+1 | |
| |\ | | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | |||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | Support more character literals | Dan Gisselquist | 2018-05-03 | 1 | -1/+9 | |
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| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 1 | -0/+3 | |
| |/ | | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST | |||||
| * | Add Verilog "automatic" keyword (ignored in synthesis) | Clifford Wolf | 2017-11-23 | 1 | -0/+1 | |
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| * | Fix ignoring of simulation timings so that invalid module parameters cause ↵ | Clifford Wolf | 2017-09-26 | 1 | -4/+0 | |
| | | | | | syntax errors | |||||
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+3 | |
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| * | Add support for SystemVerilog unique, unique0, and priority case | Clifford Wolf | 2017-02-23 | 1 | -0/+4 | |
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| * | Added SystemVerilog support for ++ and -- | Clifford Wolf | 2017-02-23 | 1 | -1/+3 | |
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| * | Add checker support to verilog front-end | Clifford Wolf | 2017-02-09 | 1 | -9/+11 | |
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| * | Add SV "rand" and "const rand" support | Clifford Wolf | 2017-02-08 | 1 | -2/+4 | |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+1 | |
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| * | Add "enum" and "typedef" lexer support | Clifford Wolf | 2017-01-17 | 1 | -0/+3 | |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -1/+0 | |
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| * | Added read_verilog -norestrict -assume-asserts | Clifford Wolf | 2016-08-26 | 1 | -1/+1 | |
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| * | Added SV "restrict" keyword | Clifford Wolf | 2016-08-24 | 1 | -1/+2 | |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -1/+5 | |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+1 | |
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| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 1 | -0/+4 | |
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| * | SystemVerilog also has assume(), added implicit -D FORMAL | Clifford Wolf | 2015-10-13 | 1 | -1/+1 | |
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| * | Fixed support for $write system task | Clifford Wolf | 2015-09-23 | 1 | -1/+1 | |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -2/+2 | |
| | | | | | Smaller this time | |||||
| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -1/+1 | |
| | | | | | This is based on work done by Larry Doolittle | |||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 | |
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| * | Ignore celldefine directive in verilog front-end | Clifford Wolf | 2015-03-25 | 1 | -0/+3 | |
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| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -2/+3 | |
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| * | Fixed handling of "//" in filenames in verilog pre-processor | Clifford Wolf | 2015-02-14 | 1 | -0/+4 | |
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| * | Ignoring more system task and functions | Clifford Wolf | 2015-01-15 | 1 | -1/+1 | |
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| * | Improved some warning messages | Clifford Wolf | 2014-12-27 | 1 | -6/+18 | |
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| * | Fixed minor bug in parsing delays | Clifford Wolf | 2014-11-24 | 1 | -1/+4 | |
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| * | Fixed two minor bugs in constant parsing | Clifford Wolf | 2014-11-24 | 1 | -2/+2 | |
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| * | Added log_warning() API | Clifford Wolf | 2014-11-09 | 1 | -6/+6 | |
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| * | Re-introduced Yosys::readsome() helper function | Clifford Wolf | 2014-10-23 | 1 | -5/+1 | |
| | | | | | (f.read() + f.gcount() made problems with lines > 16kB) | |||||
| * | Updated lexers & parsers to include prefixes | William Speirs | 2014-10-15 | 1 | -0/+359 | |
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index : iCE40/yosys | |
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