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* Encode filename unprintable charsMiodrag Milanovic2022-08-081-1/+1
* verific - make filepath handling compatible with verilog frontendMiodrag Milanovic2022-08-081-15/+29
* Setting wire upto in verific importMiodrag Milanovic2022-07-291-2/+5
* Update READMEMiodrag Milanović2022-07-281-1/+1
* Upadte documentation and changelogMiodrag Milanovic2022-07-041-0/+1
* Update to new verific extensions intefaceMiodrag Milanovic2022-06-301-3/+29
* Revert "use new verific extensions library"Miodrag Milanovic2022-06-211-70/+54
* use new verific extensions libraryMiodrag Milanovic2022-06-171-54/+70
* removed deprecated features codeMiodrag Milanovic2022-06-131-235/+0
* verific: Added "-vlog-libext" option to specify search extension for librariesMiodrag Milanovic2022-06-091-1/+16
* verific: proper file location for readmem commandsMiodrag Milanovic2022-06-041-0/+33
* fix text to fit 80 columnsMiodrag Milanovic2022-05-231-6/+9
* Update verific command file documentationMiodrag Milanovic2022-05-231-17/+19
* Use analysis mode if set in fileMiodrag Milanovic2022-05-231-2/+2
* verific: Use new value change logic also for $stable of wide signals.Jannis Harder2022-05-111-7/+29
* Merge pull request #3305 from jix/sva_value_change_logicJannis Harder2022-05-091-10/+25
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| * verific: Improve logic generated for SVA value change expressionsJannis Harder2022-05-091-10/+25
* | verific: Fix conditions of SVAs with explicit clocks within proceduresJannis Harder2022-05-033-5/+16
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* Ignore merging past ffs that we are not properly mergingMiodrag Milanovic2022-04-291-0/+1
* verific: allow memories to be inferred in loops (vhdl)Miodrag Milanovic2022-04-181-0/+1
* verific: allow memories to be inferred in loopsN. Engelhardt2022-04-151-0/+1
* Preserve internal wires for external netsMiodrag Milanovic2022-04-011-1/+1
* Fix valgrind tests when using verificMiodrag Milanovic2022-03-301-0/+8
* Properly mark modules importedMiodrag Milanovic2022-03-261-2/+2
* Import verific netlist in consistent orderMiodrag Milanovic2022-03-252-23/+27
* Remove quotes if any from attributeMiodrag Milanovic2022-02-161-1/+4
* Add ability to override verilog mode for verific -f commandMiodrag Milanovic2022-02-091-2/+44
* Use bmux for NTO1MUXMiodrag Milanovic2022-02-021-16/+2
* Add YOSYS to the implicitly defined verilog macros in verificClaire Xenia Wolf2021-12-131-1/+2
* Merge pull request #3102 from YosysHQ/claire/enumxzMiodrag Milanović2021-12-101-1/+1
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| * Fix verific import of enum values with x and/or zClaire Xenia Wolf2021-12-101-1/+1
* | Update verific.ccClaire Xen2021-12-101-4/+7
* | If direction NONE use that from first bitMiodrag Milanovic2021-12-081-0/+7
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* Make sure cell names are unique for wide operatorsMiodrag Milanovic2021-12-031-2/+2
* No need to alocate more memory than usedMiodrag Milanovic2021-11-101-1/+0
* Add "verific -cfg" commandClaire Xenia Wolf2021-11-011-2/+75
* Fix verific gclk handling for async-load FFsClaire Xenia Wolf2021-10-311-12/+67
* Enable async load dff emit by default in VerificMiodrag Milanovic2021-10-271-1/+1
* Revert "Compile option for enabling async load verific support"Miodrag Milanovic2021-10-271-4/+1
* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-251-1/+4
* Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
* Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
* Option to disable verific VHDL supportMiodrag Milanovic2021-10-202-11/+45
* Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
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| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
* | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* verific set db_infer_set_reset_registersMiodrag Milanovic2021-10-041-0/+1
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