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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-29 14:35:02 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-04-29 14:35:02 +0200 |
| commit | 422db937d44c10b850b8722dd39062650cf2db2b (patch) | |
| tree | 23864ecd938293b8301970c81e1f55e2032a5240 /frontends/verific | |
| parent | b30d90a14a6c84e5d20cb52ab008bf86503ed275 (diff) | |
| download | yosys-422db937d44c10b850b8722dd39062650cf2db2b.tar.gz yosys-422db937d44c10b850b8722dd39062650cf2db2b.tar.bz2 yosys-422db937d44c10b850b8722dd39062650cf2db2b.zip | |
Ignore merging past ffs that we are not properly merging
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 284d5db31..d19d837ff 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -987,6 +987,7 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates) for (auto cell : candidates) { + if (cell->type != ID($dff)) continue; SigBit clock = cell->getPort(ID::CLK); bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool(); database[make_pair(clock, int(clock_pol))].insert(cell); |