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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-07-29 17:10:31 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-07-29 17:10:31 +0200 |
| commit | 52a4a89265b656a97bba441ac8f5c768bdd5c73e (patch) | |
| tree | 6d44b2e80d72f0ea407c0e537517858f5a5ff470 /frontends/verific | |
| parent | 30a4218f537e76d1b3f2be0859662a7055985e27 (diff) | |
| download | yosys-52a4a89265b656a97bba441ac8f5c768bdd5c73e.tar.gz yosys-52a4a89265b656a97bba441ac8f5c768bdd5c73e.tar.bz2 yosys-52a4a89265b656a97bba441ac8f5c768bdd5c73e.zip | |
Setting wire upto in verific import
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index fd6208e86..ab527a253 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1124,6 +1124,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size()); wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex()); + wire->upto = portbus->IsUp(); import_attributes(wire->attributes, portbus, nl); bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN; @@ -1144,7 +1145,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma wire->port_output = true; } net = portbus->ElementAtIndex(i)->GetNet(); - RTLIL::SigBit bit(wire, i - wire->start_offset); + int bitidx = wire->upto ? (wire->width - 1 - (i - wire->start_offset)) : (i - wire->start_offset); + RTLIL::SigBit bit(wire, bitidx); if (net_map.count(net) == 0) net_map[net] = bit; else if (bit_input) @@ -1308,6 +1310,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size()); wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex()); + wire->upto = netbus->IsUp(); MapIter mibus; FOREACH_NET_OF_NETBUS(netbus, mibus, net) { if (net) @@ -1322,7 +1325,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma { if (netbus->ElementAtIndex(i)) { - int bitidx = i - wire->start_offset; + int bitidx = wire->upto ? (wire->width - 1 - (i - wire->start_offset)) : (i - wire->start_offset); net = netbus->ElementAtIndex(i); RTLIL::SigBit bit(wire, bitidx); |