index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
frontends
/
ast
Commit message (
Expand
)
Author
Age
Files
Lines
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
1
-5
/
+5
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
4
-39
/
+55
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
1
-5
/
+11
*
Removed left over debug code
Clifford Wolf
2014-07-28
2
-2
/
+0
*
Fixed part selects of parameters
Clifford Wolf
2014-07-28
2
-7
/
+31
*
Set results of out-of-bounds static bit/part select to undef
Clifford Wolf
2014-07-28
1
-5
/
+31
*
Fixed RTLIL code generator for part select of parameter
Clifford Wolf
2014-07-28
1
-2
/
+2
*
Fixed width detection for part selects
Clifford Wolf
2014-07-28
1
-2
/
+2
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
4
-13
/
+17
*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
1
-0
/
+3
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
3
-31
/
+30
*
Fixed signdness detection of expressions with bit- and part-selects
Clifford Wolf
2014-07-28
1
-0
/
+1
*
Added proper Design->addModule interface
Clifford Wolf
2014-07-27
1
-0
/
+1
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-5
/
+5
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-5
/
+5
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
1
-13
/
+9
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-24
/
+24
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-24
/
+24
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
1
-54
/
+19
*
Fixed two memory leaks in ast simplify
Clifford Wolf
2014-07-25
1
-1
/
+6
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
1
-7
/
+7
*
Various small fixes (from gcc compiler warnings)
Clifford Wolf
2014-07-23
1
-1
/
+1
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
1
-11
/
+0
*
SigSpec refactoring: More cleanups of old SigSpec use pattern
Clifford Wolf
2014-07-22
1
-3
/
+6
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
1
-1
/
+1
*
SigSpec refactoring: change RTLIL::SigSpec::size() to be read-only
Clifford Wolf
2014-07-22
1
-55
/
+11
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
1
-60
/
+60
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
1
-60
/
+60
*
Implemented dynamic bit-/part-select for memory writes
Clifford Wolf
2014-07-17
1
-2
/
+26
*
Added support for bit/part select to mem2reg rewriter
Clifford Wolf
2014-07-17
1
-0
/
+9
*
Added support for constant bit- or part-select for memory writes
Clifford Wolf
2014-07-17
1
-9
/
+36
*
changes in verilog frontend for new $mem/$memwr WR_EN interface
Clifford Wolf
2014-07-16
2
-7
/
+6
*
Fixed processing of initial values for block-local variables
Clifford Wolf
2014-07-11
1
-0
/
+5
*
Fixed handling of mixed real/int ternary expressions
Clifford Wolf
2014-06-25
1
-0
/
+16
*
More found_real-related fixes to AstNode::detectSignWidthWorker
Clifford Wolf
2014-06-24
1
-6
/
+6
*
fixed signdness detection for expressions with reals
Clifford Wolf
2014-06-21
1
-2
/
+8
*
Added AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf
2014-06-17
2
-0
/
+23
*
Improved handling of relational op of real values
Clifford Wolf
2014-06-17
1
-8
/
+9
*
Improved ternary support for real values
Clifford Wolf
2014-06-16
1
-13
/
+24
*
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
Clifford Wolf
2014-06-16
2
-0
/
+11
*
Added found_real feature to AstNode::detectSignWidth
Clifford Wolf
2014-06-16
2
-6
/
+11
*
Improved AstNode::realAsConst for large numbers
Clifford Wolf
2014-06-15
1
-1
/
+1
*
Improved AstNode::asReal for large integers
Clifford Wolf
2014-06-15
2
-10
/
+13
*
improved (fixed) conversion of real values to bit vectors
Clifford Wolf
2014-06-14
4
-11
/
+30
*
Fixed relational operators for const real expressions
Clifford Wolf
2014-06-14
1
-8
/
+8
*
Added support for math functions
Clifford Wolf
2014-06-14
1
-0
/
+70
*
Added handling of real-valued parameters/localparams
Clifford Wolf
2014-06-14
2
-17
/
+47
*
Implemented more real arithmetic
Clifford Wolf
2014-06-14
1
-27
/
+70
*
Implemented basic real arithmetic
Clifford Wolf
2014-06-14
3
-6
/
+51
[next]