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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 23:50:21 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 23:50:21 +0200 |
| commit | 115dd959d9dbf68aa30f8374df0e62fba8646f1e (patch) | |
| tree | e1b4ed7f3a676dcef7b73b38346fcd0418735da0 /frontends/ast | |
| parent | 9e94f41b89bca54f8a3ce2e8e54c0467a7e8c43d (diff) | |
| download | yosys-115dd959d9dbf68aa30f8374df0e62fba8646f1e.tar.gz yosys-115dd959d9dbf68aa30f8374df0e62fba8646f1e.tar.bz2 yosys-115dd959d9dbf68aa30f8374df0e62fba8646f1e.zip | |
SigSpec refactoring: More cleanups of old SigSpec use pattern
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index a51064c3e..18ae008cb 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -309,9 +309,11 @@ struct AST_INTERNAL::ProcessGenerator RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig) { sig.optimize(); - for (size_t i = 0; i < sig.chunks().size(); i++) + std::vector<RTLIL::SigChunk> chunks = sig.chunks(); + + for (int i = 0; i < SIZE(chunks); i++) { - RTLIL::SigChunk &chunk = sig.chunks_rw()[i]; + RTLIL::SigChunk &chunk = chunks[i]; if (chunk.wire == NULL) continue; @@ -329,7 +331,8 @@ struct AST_INTERNAL::ProcessGenerator chunk.wire = wire; chunk.offset = 0; } - return sig; + + return chunks; } // recursively traverse the AST an collect all assigned signals |