| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Allow $past, $stable, $rose, $fell in $global_clock blocks | Clifford Wolf | 2017-10-10 | 1 | -1/+5 |
| * | Turned a few member functions into const, esp. dumpAst(), dumpVlog(). | Udi Finkelstein | 2017-09-30 | 2 | -14/+14 |
| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 1 | -1/+1 |
| * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 1 | -17/+17 |
| * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 1 | -10/+40 |
| * | enable $bits() and $size() functions only when the SystemVerilog flag is enab... | Udi Finkelstein | 2017-09-26 | 1 | -1/+1 |
| * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 1 | -2/+26 |
| * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 1 | -1/+3 |
| * | Add $size() function. At the moment it works only on expressions, not on memo... | Udi Finkelstein | 2017-09-26 | 1 | -0/+14 |
| * | Fix generation of vlogtb output in yosys-smtbmc for "rand reg" and "rand cons... | Clifford Wolf | 2017-06-07 | 1 | -0/+7 |
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 4 | -3/+12 |
| * | Preserve string parameters | Clifford Wolf | 2017-02-23 | 1 | -2/+8 |
| * | Fix incorrect "incompatible re-declaration of wire" error in tasks/functions | Clifford Wolf | 2017-02-14 | 1 | -2/+9 |
| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 4 | -2/+6 |
| * | Fix bug in AstNode::mem2reg_as_needed_pass2() | Clifford Wolf | 2017-01-15 | 1 | -0/+2 |
| * | Fixed handling of local memories in functions | Clifford Wolf | 2017-01-05 | 1 | -2/+2 |
| * | Added handling of local memories and error for local decls in unnamed blocks | Clifford Wolf | 2017-01-04 | 1 | -1/+10 |
| * | Added Verilog $rtoi and $itor support | Clifford Wolf | 2017-01-03 | 1 | -24/+30 |
| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 2 | -13/+39 |
| * | Remember global declarations and defines accross read_verilog calls | Clifford Wolf | 2016-11-15 | 1 | -4/+2 |
| * | Fixed anonymous genblock object names | Clifford Wolf | 2016-11-04 | 1 | -1/+1 |
| * | Some fixes in handling of signed arrays | Clifford Wolf | 2016-11-01 | 2 | -0/+7 |
| * | Added avail params to ilang format, check module params in 'hierarchy -check' | Clifford Wolf | 2016-10-22 | 1 | -2/+7 |
| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 2 | -4/+4 |
| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -4/+11 |
| * | Added $past, $stable, $rose, $fell SVA functions | Clifford Wolf | 2016-09-19 | 2 | -2/+141 |
| * | Added assertpmux | Clifford Wolf | 2016-09-07 | 1 | -0/+1 |
| * | Avoid creation of bogus initial blocks for assert/assume in always @* | Clifford Wolf | 2016-09-06 | 3 | -1/+13 |
| * | Added $anyconst support to yosys-smtbmc | Clifford Wolf | 2016-08-30 | 1 | -0/+2 |
| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 2 | -5/+5 |
| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 4 | -6/+2 |
| * | Fixed bug with memories that do not have a down-to-zero data width | Clifford Wolf | 2016-08-22 | 1 | -2/+13 |
| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 3 | -7/+31 |
| * | Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog() | Clifford Wolf | 2016-08-21 | 1 | -4/+15 |
| * | Fixed finish_addr handling in $readmemh/$readmemb | Clifford Wolf | 2016-08-20 | 1 | -3/+3 |
| * | Optimize memory address port width in wreduce and memory_collect, not verilog... | Clifford Wolf | 2016-08-19 | 2 | -4/+13 |
| * | Only allow posedge/negedge with 1 bit wide signals | Clifford Wolf | 2016-08-10 | 1 | -0/+2 |
| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 2 | -0/+49 |
| * | Added "read_verilog -dump_rtlil" | Clifford Wolf | 2016-07-27 | 2 | -8/+21 |
| * | Using $initstate in "initial assume" and "initial assert" | Clifford Wolf | 2016-07-21 | 1 | -1/+6 |
| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+24 |
| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 4 | -6/+6 |
| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 4 | -7/+16 |
| * | Fixed mem assignment in left-hand-side concatenation | Clifford Wolf | 2016-07-08 | 1 | -0/+44 |
| * | A few modifications after pull request comments | Ruben Undheim | 2016-06-18 | 1 | -2/+2 |
| * | Added support for SystemVerilog packages with localparam definitions | Ruben Undheim | 2016-06-18 | 3 | -1/+16 |
| * | Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b} | Clifford Wolf | 2016-05-27 | 1 | -0/+11 |
| * | Fixed access-after-delete bug in mem2reg code | Clifford Wolf | 2016-05-27 | 2 | -6/+23 |
| * | fixed typos in error messages | Clifford Wolf | 2016-05-27 | 1 | -3/+3 |
| * | Include <cmath> in yosys.h | Clifford Wolf | 2016-05-08 | 1 | -9/+0 |
