iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Include id2ast pointers when dumping AST	Clifford Wolf	2014-03-05	1	-0/+6
*	Fixed merging of compatible wire decls in AST frontend	Clifford Wolf	2014-03-05	1	-1/+4
*	Bugfix in recursive AST simplification	Clifford Wolf	2014-03-05	1	-10/+22
*	Fixed bit-extending in $mux argument (use $bu0 instead of $pos)	Clifford Wolf	2014-02-26	1	-5/+5
*	Don't blow up constants unneccessarily in Verilog frontend	Clifford Wolf	2014-02-24	1	-1/+1
*	Fixed bug in generation of undefs for $memwr MUXes	Clifford Wolf	2014-02-22	1	-4/+6
*	Cleanups in handling of read_verilog -defer and -icells	Clifford Wolf	2014-02-20	1	-6/+7
*	Added Verilog support for "`default_nettype none"	Clifford Wolf	2014-02-17	3	-6/+13
*	Improved support for constant functions	Clifford Wolf	2014-02-16	1	-1/+50
*	Correctly convert constants to RTLIL (fixed undef handling)	Clifford Wolf	2014-02-15	1	-11/+1
*	Be more conservative with new const-function code	Clifford Wolf	2014-02-14	1	-1/+5
*	Added support for FOR loops in function calls in parameters	Clifford Wolf	2014-02-14	3	-0/+43
*	Created basic support for function calls in parameter values	Clifford Wolf	2014-02-14	4	-49/+184
*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13	2	-58/+79
*	Fixed gcc compiler warnings with release build	Clifford Wolf	2014-02-06	1	-1/+1
*	Fixed bug in sequential sat proofs and improved handling of asserts	Clifford Wolf	2014-02-04	1	-0/+2
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-0/+1
*	Added constant size expression support of sized constants	Clifford Wolf	2014-02-01	4	-0/+22
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30	1	-1/+1
*	Added read_verilog -icells option	Clifford Wolf	2014-01-29	3	-5/+11
*	Fixed algorithmic complexity of AST simplification of long expressions	Clifford Wolf	2014-01-20	3	-6/+13
*	Added $assert cell	Clifford Wolf	2014-01-19	2	-0/+92
*	Added Verilog parser support for asserts	Clifford Wolf	2014-01-19	2	-0/+2
*	Fixed typo in frontends/ast/simplify.cc	Clifford Wolf	2014-01-12	1	-1/+1
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03	1	-0/+2
*	Fixed a stupid access after delete bug	Clifford Wolf	2013-12-29	1	-1/+2
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27	1	-2/+2
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27	4	-12/+26
*	Keep strings as strings in const ternary and concat	Clifford Wolf	2013-12-05	3	-5/+25
*	Added const folding support for $signed and $unsigned	Clifford Wolf	2013-12-05	1	-0/+7
*	Added AstNode::mkconst_str API	Clifford Wolf	2013-12-05	2	-0/+18
*	Fixed generate-for (and disabled double warning for auto-wire)	Clifford Wolf	2013-12-04	1	-1/+5
*	Added support for $clog2 system function	Clifford Wolf	2013-12-04	1	-4/+20
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04	4	-2/+91
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04	3	-7/+3
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	3	-24/+37
*	Added support for local regs in named blocks	Clifford Wolf	2013-12-04	2	-0/+25
*	Fixed temp net name generation in rtlil process generator for abbreviated nam...	Clifford Wolf	2013-11-28	1	-0/+2
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28	1	-0/+1
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24	1	-1/+5
*	Added verilog frontend -ignore_redef option	Clifford Wolf	2013-11-24	2	-4/+9
*	Early wire/reg/parameter width calculation in ast/simplify	Clifford Wolf	2013-11-24	1	-0/+5
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24	3	-51/+3
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24	3	-3/+7
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
*	Fixed async proc detection in mem2reg	Clifford Wolf	2013-11-21	1	-5/+9
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	3	-87/+247
*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20	1	-4/+13
*	Do not allow memory bit select on the left side of an assignment	Clifford Wolf	2013-11-20	1	-1/+1
*	Fixed name resolution of local tasks and functions in generate block	Clifford Wolf	2013-11-20	1	-2/+16