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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-03 13:01:45 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-03 13:01:45 +0100 |
| commit | a6750b375301f2c2ebb51a2496cdf2c820b2546b (patch) | |
| tree | e3a91710abab3a7a89858426b0d17601946d8fec /frontends/ast | |
| parent | de9226a64f96a3731008218727d6b3897c58f593 (diff) | |
| download | yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.tar.gz yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.tar.bz2 yosys-a6750b375301f2c2ebb51a2496cdf2c820b2546b.zip | |
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 99d8566dc..591d027cb 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1245,6 +1245,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); + cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); return RTLIL::SigSpec(wire); } |