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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-03 00:22:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-03 00:22:17 +0100 |
| commit | fb2bf934dc6d2c969906b350c9a1b09a972bfdd7 (patch) | |
| tree | ea47a664de2af51f09fe43f3040685438f5dd2ec /frontends/ast | |
| parent | 536e20bde159db3ad8c77aeb9001a8dddde884a8 (diff) | |
| download | yosys-fb2bf934dc6d2c969906b350c9a1b09a972bfdd7.tar.gz yosys-fb2bf934dc6d2c969906b350c9a1b09a972bfdd7.tar.bz2 yosys-fb2bf934dc6d2c969906b350c9a1b09a972bfdd7.zip | |
Added correct handling of $memwr priority
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 1b6fc1d8b..e44b2d361 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1271,6 +1271,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); + + cell->parameters["\\PRIORITY"] = RTLIL::Const(RTLIL::autoidx-1); } break; |