iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Refactor code to avoid code duplication + added comments	Ruben Undheim	2018-10-20	1	-0/+5
*	Support for 'modports' for System Verilog interfaces	Ruben Undheim	2018-10-12	1	-1/+3
*	Synthesis support for SystemVerilog interfaces	Ruben Undheim	2018-10-12	1	-0/+6
*	Added -no_dump_ptr flag for AST dump options in 'read_verilog'	Udi Finkelstein	2018-08-23	1	-2/+2
*	Merge pull request #591 from hzeller/virtual-override	Clifford Wolf	2018-08-15	1	-4/+4
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\| *	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-4/+4
* \|	Merge pull request #513 from udif/pr_reg_wire_error	Clifford Wolf	2018-08-15	1	-1/+1
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\| *	Modified errors into warnings	Udi Finkelstein	2018-06-05	1	-1/+1
\| *	This PR should be the base for discussion, do not merge it yet!	Udi Finkelstein	2018-03-11	1	-1/+1
* \|	Replace -ignore_redef with -[no]overwrite	Clifford Wolf	2018-05-03	1	-1/+1
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*	Bugfix in hierarchy handling of blackbox module ports	Clifford Wolf	2018-01-05	1	-1/+1
*	Turned a few member functions into const, esp. dumpAst(), dumpVlog().	Udi Finkelstein	2017-09-30	1	-7/+7
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-0/+2
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-0/+1
*	Avoid creation of bogus initial blocks for assert/assume in always @*	Clifford Wolf	2016-09-06	1	-0/+1
*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+0
*	Another bugfix in mem2reg code	Clifford Wolf	2016-08-21	1	-1/+1
*	Added "read_verilog -dump_rtlil"	Clifford Wolf	2016-07-27	1	-3/+5
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-1/+1
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-0/+1
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	1	-1/+3
*	Fixed access-after-delete bug in mem2reg code	Clifford Wolf	2016-05-27	1	-0/+1
*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	1	-0/+2
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14	1	-1/+1
*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31	1	-1/+1
*	Fixed nested mem2reg	Clifford Wolf	2015-07-29	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	1	-0/+1
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14	1	-3/+3
*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14	1	-1/+2
*	dict/pool changes in ast	Clifford Wolf	2014-12-29	1	-4/+8
*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28	1	-2/+2
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-1/+1
*	Added support for $readmemh/$readmemb	Clifford Wolf	2014-10-26	1	-0/+1
*	Fixed handling of invalid array access in mem2reg code	Clifford Wolf	2014-10-16	1	-0/+1
*	Added AstNode::asInt()	Clifford Wolf	2014-08-21	1	-0/+1
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21	1	-0/+4
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18	1	-0/+1
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17	1	-2/+2
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14	1	-2/+3
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06	1	-0/+4
*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	1	-1/+1
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-0/+4
*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	1	-1/+1
*	Added AstNode::MEM2REG_FL_CMPLX_LHS	Clifford Wolf	2014-06-17	1	-0/+1
*	Added found_real feature to AstNode::detectSignWidth	Clifford Wolf	2014-06-16	1	-2/+2
*	improved (fixed) conversion of real values to bit vectors	Clifford Wolf	2014-06-14	1	-0/+1
*	Implemented basic real arithmetic	Clifford Wolf	2014-06-14	1	-0/+4
*	Added Verilog lexer and parser support for real values	Clifford Wolf	2014-06-13	1	-0/+2
*	Add support for cell arrays	Clifford Wolf	2014-06-07	1	-0/+1