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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-17 00:57:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-17 00:57:24 +0200 |
| commit | d491fd8c19cddb49d2feed2a873a328825c7b8f4 (patch) | |
| tree | dd6df732f746a42329a39932cdb80476597d52aa /frontends/ast/ast.h | |
| parent | 9bacc0b54c0901dfd34c2230d3295720653c0a7a (diff) | |
| download | yosys-d491fd8c19cddb49d2feed2a873a328825c7b8f4.tar.gz yosys-d491fd8c19cddb49d2feed2a873a328825c7b8f4.tar.bz2 yosys-d491fd8c19cddb49d2feed2a873a328825c7b8f4.zip | |
Use stackmap<> in AST ProcessGenerator
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index e7b075486..6ea241fa9 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -228,7 +228,7 @@ namespace AST // for expressions the resulting signal vector is returned // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false); - RTLIL::SigSpec genWidthRTLIL(int width, std::map<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL); + RTLIL::SigSpec genWidthRTLIL(int width, const std::map<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL); // compare AST nodes bool operator==(const AstNode &other) const; @@ -285,7 +285,7 @@ namespace AST_INTERNAL extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map<std::string, AST::AstNode*> current_scope; - extern std::map<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr; + extern const std::map<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr; extern RTLIL::SigSpec ignoreThisSignalsInInitial; extern AST::AstNode *current_top_block, *current_block, *current_block_child; extern AST::AstModule *current_module; |