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author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 11:21:12 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 11:21:12 +0100 |
commit | 7f1a1759d7cdbbb528c451bf8fc8baf3b7e72893 (patch) | |
tree | 24088155e5c9b3d64e8d65dfa1a3298cd714caf6 /frontends/ast/ast.h | |
parent | a8e9d37c14427527c9a810d83e183309cc5ca503 (diff) | |
download | yosys-7f1a1759d7cdbbb528c451bf8fc8baf3b7e72893.tar.gz yosys-7f1a1759d7cdbbb528c451bf8fc8baf3b7e72893.tar.bz2 yosys-7f1a1759d7cdbbb528c451bf8fc8baf3b7e72893.zip |
Added "read_verilog -nomeminit" and "nomeminit" attribute
Diffstat (limited to 'frontends/ast/ast.h')
-rw-r--r-- | frontends/ast/ast.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 3523d0754..0c1135620 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -265,13 +265,13 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire); // parametric modules are supported directly by the AST library // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions struct AstModule : RTLIL::Module { AstNode *ast; - bool nolatches, nomem2reg, mem2reg, lib, noopt, icells, autowire; + bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire; virtual ~AstModule(); virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters); virtual RTLIL::Module *clone() const; @@ -295,7 +295,7 @@ namespace AST namespace AST_INTERNAL { // internal state variables - extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; + extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map<std::string, AST::AstNode*> current_scope; extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr; |