iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add "noblackbox" attribute	Clifford Wolf	2019-04-21	1	-17/+27
*	New behavior for front-end handling of whiteboxes	Clifford Wolf	2019-04-20	1	-16/+68
*	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	1	-2/+20
*	Improve "read_verilog -dump_vlog[12]" handling of upto ranges	Clifford Wolf	2019-03-21	1	-3/+6
*	Improve read_verilog debug output capabilities	Clifford Wolf	2019-03-21	1	-9/+17
*	Fix typographical and grammatical errors and inconsistencies.	whitequark	2019-01-02	1	-2/+2
*	Various indenting fixes in AST front-end (mostly space vs tab issues)	Clifford Wolf	2018-11-04	1	-6/+3
*	Refactor code to avoid code duplication + added comments	Ruben Undheim	2018-10-20	1	-113/+99
*	Support for SystemVerilog interfaces as a port in the top level module + test...	Ruben Undheim	2018-10-20	1	-3/+105
*	Fixed memory leak	Ruben Undheim	2018-10-20	1	-0/+1
*	Documentation improvements etc.	Ruben Undheim	2018-10-13	1	-3/+28
*	Fix build error with clang	Ruben Undheim	2018-10-12	1	-1/+1
*	Support for 'modports' for System Verilog interfaces	Ruben Undheim	2018-10-12	1	-4/+36
*	Synthesis support for SystemVerilog interfaces	Ruben Undheim	2018-10-12	1	-11/+122
*	Added -no_dump_ptr flag for AST dump options in 'read_verilog'	Udi Finkelstein	2018-08-23	1	-6/+9
*	Merge pull request #513 from udif/pr_reg_wire_error	Clifford Wolf	2018-08-15	1	-1/+7
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\| *	Modified errors into warnings	Udi Finkelstein	2018-06-05	1	-0/+1
\| *	This PR should be the base for discussion, do not merge it yet!	Udi Finkelstein	2018-03-11	1	-1/+6
* \|	Convert more log_error() to log_file_error() where possible.	Henner Zeller	2018-07-20	1	-7/+6
* \|	Replace -ignore_redef with -[no]overwrite	Clifford Wolf	2018-05-03	1	-5/+13
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*	Bugfix in hierarchy handling of blackbox module ports	Clifford Wolf	2018-01-05	1	-1/+1
*	Turned a few member functions into const, esp. dumpAst(), dumpVlog().	Udi Finkelstein	2017-09-30	1	-7/+7
*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-0/+2
*	Preserve string parameters	Clifford Wolf	2017-02-23	1	-2/+8
*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-0/+1
*	Added support for hierarchical defparams	Clifford Wolf	2016-11-15	1	-2/+7
*	Remember global declarations and defines accross read_verilog calls	Clifford Wolf	2016-11-15	1	-4/+2
*	Added avail params to ilang format, check module params in 'hierarchy -check'	Clifford Wolf	2016-10-22	1	-2/+7
*	Avoid creation of bogus initial blocks for assert/assume in always @*	Clifford Wolf	2016-09-06	1	-0/+1
*	Removed $predict again	Clifford Wolf	2016-08-28	1	-1/+0
*	Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()	Clifford Wolf	2016-08-21	1	-4/+15
*	Added "read_verilog -dump_rtlil"	Clifford Wolf	2016-07-27	1	-5/+16
*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-1/+1
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-0/+1
*	A few modifications after pull request comments	Ruben Undheim	2016-06-18	1	-2/+2
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	1	-0/+12
*	Include <cmath> in yosys.h	Clifford Wolf	2016-05-08	1	-9/+0
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Fixed handling of parameters and const functions in casex/casez pattern	Clifford Wolf	2016-04-21	1	-1/+10
*	Fixed some visual studio warnings	Clifford Wolf	2016-02-13	1	-1/+1
*	Fixed segfault in AstNode::asReal	Clifford Wolf	2015-09-25	1	-1/+1
*	Fixed AstNode::mkconst_bits() segfault on zero-sized constant	Clifford Wolf	2015-09-24	1	-1/+1
*	Another block of spelling fixes	Larry Doolittle	2015-08-14	1	-4/+4
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26	1	-0/+1
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14	1	-2/+6
*	Creating $meminit cells in verilog front-end	Clifford Wolf	2015-02-14	1	-1/+2
*	Added global yosys_celltypes	Clifford Wolf	2014-12-29	1	-1/+1
*	dict/pool changes in ast	Clifford Wolf	2014-12-29	1	-0/+4
*	Changed more code to dict<> and pool<>	Clifford Wolf	2014-12-28	1	-1/+1