iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix abc9 with (* keep *) wires	Eddie Hung	2019-04-23	1	-6/+14
*	Temporarily remove 'r' extension	Eddie Hung	2019-04-22	1	-77/+7
*	Allow POs to be PIs in XAIG	Eddie Hung	2019-04-22	1	-7/+4
*	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-22	1	-0/+8
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\| *	Add support for zero-width signals to Verilog back-end, fixes #948	Clifford Wolf	2019-04-22	1	-0/+8
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-20	1	-1/+1
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\| *	Merge pull request #943 from YosysHQ/clifford/whitebox	Clifford Wolf	2019-04-20	8	-12/+12
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\| \| *	Revert "write_json to not write contents (cells/wires) of whiteboxes"	Eddie Hung	2019-04-18	1	-59/+56
\| \| *	write_json to not write contents (cells/wires) of whiteboxes	Eddie Hung	2019-04-18	1	-56/+59
\| * \|	Change "ne" to "neq" in btor2 output	Clifford Wolf	2019-04-19	1	-1/+1
* \| \|	Fixes for simple_abc9 tests	Eddie Hung	2019-04-19	1	-4/+8
* \| \|	Do not assume inst_module is always present	Eddie Hung	2019-04-19	1	-12/+9
* \| \|	ignore_boxes -> holes_mode	Eddie Hung	2019-04-19	1	-6/+5
* \| \|	Add flop support for write_xaiger	Eddie Hung	2019-04-18	1	-11/+83
* \| \|	Spelling	Eddie Hung	2019-04-18	1	-1/+1
* \| \|	Use new -wb flag for ABC flow	Eddie Hung	2019-04-18	1	-29/+31
* \| \|	write_json to not write contents (cells/wires) of whiteboxes	Eddie Hung	2019-04-18	1	-56/+59
* \| \|	Merge remote-tracking branch 'origin/clifford/whitebox' into xaig	Eddie Hung	2019-04-18	8	-12/+12
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\| * \|	Add "whitebox" attribute, add "read_verilog -wb"	Clifford Wolf	2019-04-18	8	-12/+12
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* \|	Fix $anyseq warning and cleanup	Eddie Hung	2019-04-17	1	-16/+7
* \|	Cope with inout ports	Eddie Hung	2019-04-17	1	-1/+15
* \|	Stop topological sort at abc_flop_q	Eddie Hung	2019-04-17	1	-7/+13
* \|	Remove init* from xaiger, also topo-sort cells for box flow	Eddie Hung	2019-04-17	1	-95/+157
* \|	Optimise	Eddie Hung	2019-04-16	1	-4/+3
* \|	CIs before PIs; also sort each cell's connections before iterating	Eddie Hung	2019-04-16	1	-5/+7
* \|	Port from xc7mux branch	Eddie Hung	2019-04-16	1	-37/+109
* \|	Output __const0__ and __const1__ CIs	Eddie Hung	2019-04-12	1	-7/+10
* \|	ci_bits and co_bits now a list, order is important for ABC	Eddie Hung	2019-04-12	1	-24/+34
* \|	WIP	Eddie Hung	2019-04-12	1	-14/+68
* \|	Add non-input bits driven by unrecognised cells as ci_bits	Eddie Hung	2019-04-10	1	-1/+1
* \|	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	9	-62/+305
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\| *	Refine memory support to deal with general Verilog memory definitions.	Jim Lawson	2019-04-01	1	-30/+173
\| *	Add support for memory initialization to write_btor	Clifford Wolf	2019-03-23	1	-0/+53
\| *	Fix BTOR output tags syntax in writye_btor	Clifford Wolf	2019-03-23	1	-2/+1
\| *	Fix smtbmc.py handling of zero appended steps	Clifford Wolf	2019-03-14	1	-5/+5
\| *	Fix a syntax bug in ilang backend related to process case statements	Clifford Wolf	2019-03-14	1	-1/+1
\| *	Merge pull request #869 from cr1901/win-shell	Clifford Wolf	2019-03-14	1	-1/+17
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\| \| *	Install launcher executable when running yosys-smtbmc on Windows.	William D. Jones	2019-03-13	1	-1/+17
\| * \|	Improve determinism of IdString DB for similar scripts	Clifford Wolf	2019-03-11	1	-0/+4
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\| *	Fix signed $shift/$shiftx handling in write_smt2	Clifford Wolf	2019-03-09	1	-1/+2
\| *	Use SVA label in smt export if available	Clifford Wolf	2019-03-07	1	-2/+2
\| *	Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails	Jim Lawson	2019-03-04	1	-2/+1
\| *	Fix "write_edif -gndvccy"	Clifford Wolf	2019-03-01	1	-1/+1
\| *	Add "write_verilog -siminit"	Clifford Wolf	2019-02-28	1	-2/+11
\| *	Reduce amount of trailing whitespace in code base	Larry Doolittle	2019-02-28	1	-3/+3
\| *	Merge pull request #827 from ucb-bar/firrtlfixes	Clifford Wolf	2019-02-28	1	-8/+20
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\| \| *	Fix FIRRTL to Verilog process instance subfield assignment.	Jim Lawson	2019-02-25	1	-8/+20
\| * \|	Fix smt2 code generation for partially initialized memowy words, fixes #831	Clifford Wolf	2019-02-28	1	-4/+11
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* \|	write_xaiger to behave for undriven/unused inouts	Eddie Hung	2019-02-26	1	-23/+25
* \|	write_xaiger duplicate inout port into out port with $inout.out suffix	Eddie Hung	2019-02-25	1	-3/+26