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* Support filename rewrite in backendsBen Widawsky2019-06-184-0/+4
| | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* Add timescale and generated-by header to yosys-smtbmc MkVcdClifford Wolf2019-06-161-0/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of offset and upto module ports in write_blif, fixes #1040Clifford Wolf2019-05-251-6/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add proper error message for btor recursion_guardClifford Wolf2019-05-241-1/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix static shift operands, neg result type, minor formattingJim Lawson2019-05-211-3/+7
| | | | | | Static shift operands must be constants. The result of FIRRTL's neg operator is signed. Fix poor indentation for gen_read().
* Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-081-1/+2
|\ | | | | Fix all warnings that occurred when compiling with gcc9
| * Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-1/+2
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* | Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "real" keyword to ilang formatClifford Wolf2019-05-061-1/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve write_verilog specify supportClifford Wolf2019-05-041-15/+71
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-25/+62
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| * Re-indent firrtl.cc:struct memory - no functional change.Jim Lawson2019-05-011-25/+25
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| * Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-011-4/+41
| | | | | | | | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
* | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specify2/$specify3 support to write_verilogClifford Wolf2019-04-231-0/+47
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add support for $assert/$assume/$cover to write_verilogClifford Wolf2019-04-231-0/+10
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for zero-width signals to Verilog back-end, fixes #948Clifford Wolf2019-04-221-0/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #943 from YosysHQ/clifford/whiteboxClifford Wolf2019-04-208-12/+12
|\ | | | | [WIP] Add "whitebox" attribute, add "read_verilog -wb"
| * Revert "write_json to not write contents (cells/wires) of whiteboxes"Eddie Hung2019-04-181-59/+56
| | | | | | | | This reverts commit 4ef03e19a8eafc324d3442f0642abf858071fdd4.
| * write_json to not write contents (cells/wires) of whiteboxesEddie Hung2019-04-181-56/+59
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| * Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-188-12/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Change "ne" to "neq" in btor2 outputClifford Wolf2019-04-191-1/+1
|/ | | | | | | we need to do this because they changed the parser: https://github.com/Boolector/btor2tools/commit/e97fc9cedabadeec4f621de22096e514f862c690 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Refine memory support to deal with general Verilog memory definitions.Jim Lawson2019-04-011-30/+173
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* Add support for memory initialization to write_btorClifford Wolf2019-03-231-0/+53
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix BTOR output tags syntax in writye_btorClifford Wolf2019-03-231-2/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix smtbmc.py handling of zero appended stepsClifford Wolf2019-03-141-5/+5
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix a syntax bug in ilang backend related to process case statementsClifford Wolf2019-03-141-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #869 from cr1901/win-shellClifford Wolf2019-03-141-1/+17
|\ | | | | Install launcher executable when running yosys-smtbmc on Windows.
| * Install launcher executable when running yosys-smtbmc on Windows.William D. Jones2019-03-131-1/+17
| | | | | | | | Signed-off-by: William D. Jones <thor0505@comcast.net>
* | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-0/+4
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix signed $shift/$shiftx handling in write_smt2Clifford Wolf2019-03-091-1/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use SVA label in smt export if availableClifford Wolf2019-03-071-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-2/+1
| | | | Mark dff_init.v as expected to fail since it uses "initial value".
* Fix "write_edif -gndvccy"Clifford Wolf2019-03-011-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_verilog -siminit"Clifford Wolf2019-02-281-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-281-3/+3
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* Merge pull request #827 from ucb-bar/firrtlfixesClifford Wolf2019-02-281-8/+20
|\ | | | | Fix FIRRTL to Verilog process instance subfield assignment.
| * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-8/+20
| | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
* | Fix smt2 code generation for partially initialized memowy words, fixes #831Clifford Wolf2019-02-281-4/+11
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
| | | | per @cliffordwolf
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-172-86/+246
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| * Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
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| * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-48/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
| * Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
| |\ | | | | | | write_verilog: correctly emit asynchronous transparent ports
| | * write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
* | | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
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* | | RefactorEddie Hung2019-02-061-21/+5
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* | | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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* / Add missing blackslash-to-slash convertion to smtio.py (matching ↵Clifford Wolf2019-02-061-1/+1
|/ | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ | | | | write_verilog: write $tribuf cell as ternary
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