| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position | Clifford Wolf | 2019-07-09 | 1 | -3/+2 |
| * | Merge pull request #1163 from whitequark/more-case-attrs | Clifford Wolf | 2019-07-09 | 1 | -6/+11 |
| * | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 1 | -0/+5 |
| * | Improve BTOR2 handling of undriven wires | Clifford Wolf | 2019-06-26 | 1 | -3/+27 |
| * | Escape scope names starting with dollar sign in smtio.py | Clifford Wolf | 2019-06-26 | 1 | -1/+4 |
| * | Fix json formatting | Miodrag Milanovic | 2019-06-21 | 1 | -1/+1 |
| * | Add upto and offset to JSON ports | Miodrag Milanovic | 2019-06-21 | 1 | -0/+4 |
| * | Added JSON upto and offset | Clifford Wolf | 2019-06-21 | 1 | -0/+4 |
| * | Fix gcc invalidation behaviour for write_aiger | Eddie Hung | 2019-06-20 | 1 | -1/+2 |
| * | Support filename rewrite in backends | Ben Widawsky | 2019-06-18 | 4 | -0/+4 |
| * | Add timescale and generated-by header to yosys-smtbmc MkVcd | Clifford Wolf | 2019-06-16 | 1 | -0/+2 |
| * | Fix handling of offset and upto module ports in write_blif, fixes #1040 | Clifford Wolf | 2019-05-25 | 1 | -6/+20 |
| * | Add proper error message for btor recursion_guard | Clifford Wolf | 2019-05-24 | 1 | -1/+7 |
| * | Fix static shift operands, neg result type, minor formatting | Jim Lawson | 2019-05-21 | 1 | -3/+7 |
| * | Merge pull request #991 from kristofferkoch/gcc9-warnings | Clifford Wolf | 2019-05-08 | 1 | -1/+2 |
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| | * | Fix all warnings that occurred when compiling with gcc9 | Kristoffer Ellersgaard Koch | 2019-05-08 | 1 | -1/+2 |
| * | | Fix handling of partial init attributes in write_verilog, fixes #997 | Clifford Wolf | 2019-05-07 | 1 | -1/+2 |
| * | | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 1 | -1/+4 |
| * | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -15/+71 |
| * | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -25/+62 |
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| | * | Re-indent firrtl.cc:struct memory - no functional change. | Jim Lawson | 2019-05-01 | 1 | -25/+25 |
| | * | Fix #938 - Crash occurs in case when use write_firrtl command | Jim Lawson | 2019-05-01 | 1 | -4/+41 |
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| * | | Add $specify2/$specify3 support to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+47 |
| * | | Add support for $assert/$assume/$cover to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+10 |
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| * | Add support for zero-width signals to Verilog back-end, fixes #948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 |
| * | Merge pull request #943 from YosysHQ/clifford/whitebox | Clifford Wolf | 2019-04-20 | 8 | -12/+12 |
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| | * | Revert "write_json to not write contents (cells/wires) of whiteboxes" | Eddie Hung | 2019-04-18 | 1 | -59/+56 |
| | * | write_json to not write contents (cells/wires) of whiteboxes | Eddie Hung | 2019-04-18 | 1 | -56/+59 |
| | * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 8 | -12/+12 |
| * | | Change "ne" to "neq" in btor2 output | Clifford Wolf | 2019-04-19 | 1 | -1/+1 |
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| * | Refine memory support to deal with general Verilog memory definitions. | Jim Lawson | 2019-04-01 | 1 | -30/+173 |
| * | Add support for memory initialization to write_btor | Clifford Wolf | 2019-03-23 | 1 | -0/+53 |
| * | Fix BTOR output tags syntax in writye_btor | Clifford Wolf | 2019-03-23 | 1 | -2/+1 |
| * | Fix smtbmc.py handling of zero appended steps | Clifford Wolf | 2019-03-14 | 1 | -5/+5 |
| * | Fix a syntax bug in ilang backend related to process case statements | Clifford Wolf | 2019-03-14 | 1 | -1/+1 |
| * | Merge pull request #869 from cr1901/win-shell | Clifford Wolf | 2019-03-14 | 1 | -1/+17 |
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| | * | Install launcher executable when running yosys-smtbmc on Windows. | William D. Jones | 2019-03-13 | 1 | -1/+17 |
| * | | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 1 | -0/+4 |
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| * | Fix signed $shift/$shiftx handling in write_smt2 | Clifford Wolf | 2019-03-09 | 1 | -1/+2 |
| * | Use SVA label in smt export if available | Clifford Wolf | 2019-03-07 | 1 | -2/+2 |
| * | Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails | Jim Lawson | 2019-03-04 | 1 | -2/+1 |
| * | Fix "write_edif -gndvccy" | Clifford Wolf | 2019-03-01 | 1 | -1/+1 |
| * | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 1 | -2/+11 |
| * | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 1 | -3/+3 |
| * | Merge pull request #827 from ucb-bar/firrtlfixes | Clifford Wolf | 2019-02-28 | 1 | -8/+20 |
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| | * | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 1 | -8/+20 |
| * | | Fix smt2 code generation for partially initialized memowy words, fixes #831 | Clifford Wolf | 2019-02-28 | 1 | -4/+11 |
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| * | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 |
| * | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 2 | -86/+246 |
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