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* Fix "write_edif -gndvccy"Clifford Wolf2019-03-011-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_verilog -siminit"Clifford Wolf2019-02-281-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-281-3/+3
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* Merge pull request #827 from ucb-bar/firrtlfixesClifford Wolf2019-02-281-8/+20
|\ | | | | Fix FIRRTL to Verilog process instance subfield assignment.
| * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-8/+20
| | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
* | Fix smt2 code generation for partially initialized memowy words, fixes #831Clifford Wolf2019-02-281-4/+11
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
| | | | per @cliffordwolf
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-172-86/+246
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| * Removed unused variables, functions.Jim Lawson2019-02-151-20/+0
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| * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-48/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
| * Merge pull request #802 from whitequark/write_verilog_async_mem_portsClifford Wolf2019-02-121-38/+41
| |\ | | | | | | write_verilog: correctly emit asynchronous transparent ports
| | * write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes two related issues: * For asynchronous ports, clock is no longer added to domain list. (This would lead to absurd constructs like `always @(posedge 0)`. * The logic to distinguish synchronous and asynchronous ports is changed to correctly use or avoid clock in all cases. Before this commit, the following RTLIL snippet (after memory_collect) cell $memrd $2 parameter \MEMID "\\mem" parameter \ABITS 2 parameter \WIDTH 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 1 parameter \TRANSPARENT 1 connect \CLK 1'0 connect \EN 1'1 connect \ADDR \mem_r_addr connect \DATA \mem_r_data end would lead to invalid Verilog: reg [1:0] _0_; always @(posedge 1'h0) begin _0_ <= mem_r_addr; end assign mem_r_data = mem[_0_]; Note that there are two potential pitfalls remaining after this change: * For asynchronous ports, the \EN input and \TRANSPARENT parameter are silently ignored. (Per discussion in #760 this is the correct behavior.) * For synchronous transparent ports, the \EN input is ignored. This matches the behavior of the $mem simulation cell. Again, see #760.
* | | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
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* | | RefactorEddie Hung2019-02-061-21/+5
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* | | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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* / Add missing blackslash-to-slash convertion to smtio.py (matching ↵Clifford Wolf2019-02-061-1/+1
|/ | | | | | Smt2Worker::get_id() behavior) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
|\ | | | | write_verilog: write $tribuf cell as ternary
| * write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
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* | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* Add "write_edif -gndvccy"Clifford Wolf2019-01-171-5/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-024-7/+7
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-3/+3
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* Minor style fixesClifford Wolf2018-12-182-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add btor ops for $mul, $div, $mod and $concatmakaimann2018-12-172-2/+38
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* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation corresponds to the following Verilog, which is lifted straight from simlib.v: module \\$shift (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 0; parameter B_WIDTH = 0; parameter Y_WIDTH = 0; input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; generate if (B_SIGNED) begin:BLOCK1 assign Y = $signed(B) < 0 ? A << -B : A >> B; end else begin:BLOCK2 assign Y = A >> B; end endgenerate endmodule
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
|\ | | | | select: print selection if a -assert-* flag causes an error
| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
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* | Merge pull request #729 from whitequark/write_verilog_initialClifford Wolf2018-12-161-0/+2
|\ \ | | | | | | write_verilog: correctly map RTLIL `sync init`
| * | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* | Add yosys-smtbmc support for btor witnessClifford Wolf2018-12-101-15/+100
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "yosys-smtbmc --btorwit" skeletonClifford Wolf2018-12-081-1/+19
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix btor init value handlingClifford Wolf2018-12-081-9/+13
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "write_aiger -I -O -B"Clifford Wolf2018-11-121-2/+36
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #693 from YosysHQ/rlimitClifford Wolf2018-11-071-8/+11
|\ | | | | improve rlimit handling in smtio.py
| * Limit stack size to 16 MB on DarwinClifford Wolf2018-11-071-1/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix for improved smtio.py rlimit codeClifford Wolf2018-11-061-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve stack rlimit code in smtio.pyClifford Wolf2018-11-061-8/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Run solver in non-incremental mode whem smtio.py is configured for ↵Clifford Wolf2018-11-061-3/+12
|/ | | | | | non-incremental solving Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Use conservative stack size for SMT2 on MacOSArjen Roodselaar2018-11-041-1/+6
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* Add proper error message for when smtbmc "append" failsClifford Wolf2018-11-041-2/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for signed $shift/$shiftx in smt2 back-endClifford Wolf2018-11-011-1/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* adding offset info to memoriesrafaeltp2018-10-181-1/+1
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* adding offset info to memoriesrafaeltp2018-10-181-2/+3
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* Merge pull request #663 from aman-goel/masterClifford Wolf2018-10-171-32/+51
|\ | | | | Update to .smv backend
| * Minor updateAman Goel2018-10-151-1/+1
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| * Update to .smv backendAman Goel2018-10-011-33/+52
| | | | | | | | Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
* | Add "write_edif -attrprop"Clifford Wolf2018-10-051-11/+28
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* added prefix to FDirection constants, fixing windows buildMiodrag Milanovic2018-09-211-11/+11
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* Fixed typo in "verilog_write" help messageacw12512018-09-181-3/+3
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