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* Fixed "write_verilog -attr2comment" handling of "*/" in stringsClifford Wolf2015-02-131-2/+4
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* Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-011-11/+10
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* Shorter "dump" optionsClifford Wolf2015-01-311-4/+4
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* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-242-2/+4
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* Added dict/pool.sort()Clifford Wolf2015-01-242-50/+26
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* Cosmetic changes in verilog output formatClifford Wolf2015-01-021-5/+10
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* Fixed memory->start_offset handlingClifford Wolf2015-01-011-0/+2
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* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-262-42/+42
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-1/+1
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* Various fixes and improvements in "write_smt2 -bv"Clifford Wolf2014-12-253-11/+43
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* Various fixes and improvements in write_smt2Clifford Wolf2014-12-252-32/+88
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* Added support for most BV cell types to write_smt2Clifford Wolf2014-12-251-14/+221
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* Added "write_smt2 -bv" and other write_smt2 improvementsClifford Wolf2014-12-251-172/+153
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* Added write_smt2 (only gate level logic supported so far)Clifford Wolf2014-12-242-0/+353
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
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* Added $dffe support to write_verilogClifford Wolf2014-12-201-3/+14
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* Fixed another bug in write_blif handling of $lut cellsClifford Wolf2014-12-191-1/+1
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* Fixed writing of $lut cells in BLIF backendClifford Wolf2014-12-171-7/+7
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* Added "write_blif -undef" and support for special "-" true/false/undef typeClifford Wolf2014-12-141-13/+33
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* Added "write_blif -blackbox"Clifford Wolf2014-12-141-2/+16
| | | | | based on code by Eddie Hung from https://github.com/eddiehung/yosys/commit/1e481661cb4a4
* Added "blif -unbuf" featureClifford Wolf2014-12-141-0/+19
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* Added log_warning() APIClifford Wolf2014-11-091-1/+1
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* Fixed generation of temp names in verilog backendClifford Wolf2014-11-071-4/+5
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-102-2/+2
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* namespace YosysClifford Wolf2014-09-278-42/+28
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* Merge branch 'master' of https://github.com/cliffordwolf/yosys into btorAhmed Irfan2014-09-2212-1284/+1139
|\ | | | | | | | | | | | | | | | | added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
| * Sorting of object names in ilang backendClifford Wolf2014-09-192-21/+49
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| * Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-061-1/+2
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| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
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| * Removed $bu0 cell typeClifford Wolf2014-09-041-1/+0
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| * Using $pos models for $bu0Clifford Wolf2014-09-031-16/+1
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| * Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-011-1/+2
| | | | | | | | RTLIL::SigChunk::data
| * Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-231-4/+4
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| * Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-239-582/+579
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| * Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-161-4/+4
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| * Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-161-4/+40
| | | | | | | | $_OAI4_
| * Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-151-2/+2
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| * Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-152-2/+2
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| * Refactoring of CellType classClifford Wolf2014-08-141-10/+28
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| * Be more conservative with printing decimal numbers in verilog backendClifford Wolf2014-08-021-2/+3
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| * Improved verilog output for ordinary $mux cellsClifford Wolf2014-08-021-3/+19
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| * No implicit conversion from IdString to anything elseClifford Wolf2014-08-024-5/+5
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| * More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-024-19/+19
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| * Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-314-86/+86
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| * Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-312-4/+8
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| * Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-292-338/+0
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| * Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-1/+3
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| * Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-9/+22
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| * Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-281-0/+2
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| * Using log_assert() instead of assert()Clifford Wolf2014-07-287-11/+5
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