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Fix formatting for msys2 mingw build using GetSize
Miodrag Milanovic
2019-08-01
1
-6
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+6
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Merge pull request #1203 from whitequark/write_verilog-zero-width-values
Clifford Wolf
2019-07-18
1
-1
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+2
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write_verilog: dump zero width constants correctly.
whitequark
2019-07-16
1
-1
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+2
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Remove old $pmux_safe code from write_verilog
Clifford Wolf
2019-07-17
1
-5
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+4
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smt: handle failure of setrlimit syscall
N. Engelhardt
2019-07-15
1
-1
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+5
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Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
Clifford Wolf
2019-07-11
1
-2
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+8
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write_verilog: write RTLIL::Sa aka - as Verilog ?.
whitequark
2019-07-09
1
-2
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+8
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abc_flop to also get topologically sorted
Eddie Hung
2019-07-10
1
-11
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+10
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Fix clk_pol for FD*_1
Eddie Hung
2019-07-10
1
-1
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+0
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Fix spacing
Eddie Hung
2019-07-10
1
-1
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+1
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Change how to specify flops to ABC again
Eddie Hung
2019-07-10
1
-10
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+20
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Use split_tokens()
Eddie Hung
2019-07-10
1
-17
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+11
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-07-10
3
-15
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+34
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Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position
Clifford Wolf
2019-07-09
1
-3
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+2
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write_verilog: fix placement of case attributes. NFC.
whitequark
2019-07-09
1
-3
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+2
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Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore
Eddie Hung
2019-07-09
1
-4
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+6
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Rename __builtin_bswap32 -> bswap32
Eddie Hung
2019-07-09
1
-4
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+6
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verilog_backend: dump attributes on SwitchRule.
whitequark
2019-07-08
1
-0
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+1
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verilog_backend: dump attributes on CaseRule, as comments.
whitequark
2019-07-08
1
-6
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+10
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Allow attributes on individual switch cases in RTLIL.
whitequark
2019-07-08
1
-0
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+5
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write_xaiger to treat unknown cell connections as keep-s
Eddie Hung
2019-07-02
1
-6
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+14
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Safe side: all flops have different mergeability class
Eddie Hung
2019-07-02
1
-1
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+1
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Refactor and cope with new abc_flop format
Eddie Hung
2019-07-01
1
-16
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+38
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-07-01
7
-102
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+204
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Add generic __builtin_bswap32 function
Eddie Hung
2019-06-28
1
-0
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+15
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Also fix write_aiger for UB
Eddie Hung
2019-06-28
1
-26
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+26
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Fix more potential for undefined behaviour due to container invalidation
Eddie Hung
2019-06-28
1
-6
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+10
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Refactor for one "abc_carry" attribute on module
Eddie Hung
2019-06-27
1
-42
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+40
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Merge origin/master
Eddie Hung
2019-06-27
2
-4
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+31
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Improve debugging message for comb loops
Eddie Hung
2019-06-26
1
-4
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+6
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-24
1
-0
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+4
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Fix json formatting
Miodrag Milanovic
2019-06-21
1
-1
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+1
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Add upto and offset to JSON ports
Miodrag Milanovic
2019-06-21
1
-0
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+4
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Carry in/out box ordering now move to end, not swap with end
Eddie Hung
2019-06-22
1
-26
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+34
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-21
1
-0
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+4
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Added JSON upto and offset
Clifford Wolf
2019-06-21
1
-0
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+4
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Fix gcc invalidation behaviour for write_aiger
Eddie Hung
2019-06-20
1
-1
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+2
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Replace assert with error message
Eddie Hung
2019-06-21
1
-1
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+2
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Add log_push()/log_pop() inside write_xaiger
Eddie Hung
2019-06-21
1
-0
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+4
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One more workaround for gcc-4.8
Eddie Hung
2019-06-21
1
-3
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+4
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No point logging constant bit
Eddie Hung
2019-06-21
1
-1
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+1
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Move comment
Eddie Hung
2019-06-21
1
-2
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+3
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Fix spacing
Eddie Hung
2019-06-20
1
-1
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+1
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Refactor bit2aig for less lookups
Eddie Hung
2019-06-20
1
-24
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+27
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Fix gcc invalidation behaviour for write_aiger
Eddie Hung
2019-06-20
1
-1
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+2
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Fix gcc error, due to dict invalidation during recursion
Eddie Hung
2019-06-20
1
-2
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+3
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write_xaiger to flatten 1'bx/1'bz to 1'b0 again
Eddie Hung
2019-06-20
1
-2
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+4
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Fix different abc9 test
Eddie Hung
2019-06-20
1
-2
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+3
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Fix broken abc9.v test due to inout being 1'bx
Eddie Hung
2019-06-20
1
-2
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+11
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-20
5
-0
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+6
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