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* Add log_assert to ensure no loopsEddie Hung2019-06-041-1/+15
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* Only toposort builtin and abc typesEddie Hung2019-06-041-6/+9
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* When creating new holes cell, inherit parameters tooEddie Hung2019-06-031-1/+3
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* ABC9 to understand flopsEddie Hung2019-05-311-46/+27
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* Merge branch 'xaig' into xc7muxEddie Hung2019-05-311-8/+79
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| * Fix abc9 with (* keep *) wiresEddie Hung2019-04-231-6/+14
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| * Revert "Temporarily remove 'r' extension"Eddie Hung2019-04-221-7/+77
| | | | | | | | This reverts commit eaf3c247729365cec776e147f380ce59f7dccd4d.
* | Fix issue where keep signal became PI, but also box was adding CI driverEddie Hung2019-05-301-5/+19
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* | Do not re-sort box_module portsEddie Hung2019-05-301-4/+6
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* | Carry in/out to be the last input/output for chains to be preservedEddie Hung2019-05-301-0/+38
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* | Fix abc_test024Eddie Hung2019-05-291-4/+5
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* | Fix for abc9_test022Eddie Hung2019-05-281-2/+6
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* | Small improvementEddie Hung2019-05-281-4/+2
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* | Update from masterEddie Hung2019-05-281-59/+56
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* | Map file to include boxes not CI/COEddie Hung2019-05-271-45/+38
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* | Instantiate cell type (from sym file) otherwise 'clean' warningsEddie Hung2019-05-271-2/+4
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* | Add 'cinput' and 'coutput' to symbols file for boxesEddie Hung2019-05-271-34/+24
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* | Fix "a" connectivityEddie Hung2019-05-261-5/+30
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* | Fix padding, remove CIs from undriven_bits before erasing undriven POsEddie Hung2019-05-261-14/+8
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* | Fix "a" extensionEddie Hung2019-05-261-8/+18
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* | Fix "write_xaiger", and to write each box contents into holesEddie Hung2019-05-251-39/+62
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* | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-252-7/+27
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| * | Fix handling of offset and upto module ports in write_blif, fixes #1040Clifford Wolf2019-05-251-6/+20
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add proper error message for btor recursion_guardClifford Wolf2019-05-241-1/+7
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7muxEddie Hung2019-05-231-3/+7
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| * | Fix static shift operands, neg result type, minor formattingJim Lawson2019-05-211-3/+7
| | | | | | | | | | | | | | | | | | Static shift operands must be constants. The result of FIRRTL's neg operator is signed. Fix poor indentation for gen_read().
* | | Pad all boxes so that all input/output connections specifiedEddie Hung2019-05-211-22/+67
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-213-11/+129
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| * | Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-081-1/+2
| |\ \ | | | | | | | | Fix all warnings that occurred when compiling with gcc9
| | * | Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-1/+2
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| * | | Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add "real" keyword to ilang formatClifford Wolf2019-05-061-1/+4
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Improve write_verilog specify supportClifford Wolf2019-05-041-15/+71
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-25/+62
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| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add $specify2/$specify3 support to write_verilogClifford Wolf2019-04-231-0/+47
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Add support for $assert/$assume/$cover to write_verilogClifford Wolf2019-04-231-0/+10
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-05-021-25/+62
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| * | | Re-indent firrtl.cc:struct memory - no functional change.Jim Lawson2019-05-011-25/+25
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| * | | Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-011-4/+41
| |/ / | | | | | | | | | | | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
* | | Remove topo sort no-loop assertion, with testEddie Hung2019-04-241-13/+0
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* | | Fix abc9 with (* keep *) wiresEddie Hung2019-04-231-6/+14
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* | Temporarily remove 'r' extensionEddie Hung2019-04-221-77/+7
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* | Allow POs to be PIs in XAIGEddie Hung2019-04-221-7/+4
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-221-0/+8
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| * Add support for zero-width signals to Verilog back-end, fixes #948Clifford Wolf2019-04-221-0/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-201-1/+1
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| * Merge pull request #943 from YosysHQ/clifford/whiteboxClifford Wolf2019-04-208-12/+12
| |\ | | | | | | [WIP] Add "whitebox" attribute, add "read_verilog -wb"
| | * Revert "write_json to not write contents (cells/wires) of whiteboxes"Eddie Hung2019-04-181-59/+56
| | | | | | | | | | | | This reverts commit 4ef03e19a8eafc324d3442f0642abf858071fdd4.
| | * write_json to not write contents (cells/wires) of whiteboxesEddie Hung2019-04-181-56/+59
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