| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 1 | -42/+0 |
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| | * | Compute abc_scc_break and move CI/CO outside of each abc9 | Eddie Hung | 2019-08-16 | 1 | -42/+0 |
| * | | Fix various NDEBUG compiler warnings, closes #1255 | Clifford Wolf | 2019-08-13 | 1 | -1/+1 |
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| * | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 9 | -33/+33 |
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| | * | substr() -> compare() | Eddie Hung | 2019-08-07 | 5 | -6/+6 |
| | * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 4 | -12/+12 |
| | * | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 2 | -106/+240 |
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| | * | | Use IdString::begins_with() | Eddie Hung | 2019-08-06 | 1 | -2/+2 |
| | * | | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-06 | 1 | -5/+5 |
| | * | | Use State::S{0,1} | Eddie Hung | 2019-08-06 | 3 | -6/+6 |
| | * | | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 2 | -2/+2 |
| * | | | Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell | Clifford Wolf | 2019-08-10 | 1 | -1/+1 |
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| | * \ \ | Merge branch 'master' into firrtl_err_on_unsupported_cell | Jim Lawson | 2019-08-07 | 9 | -116/+287 |
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| | * | | | Call log_error() instead of log_warning() on unsupported cell type in FIRRTL ... | Jim Lawson | 2019-07-24 | 1 | -1/+1 |
| * | | | | Run "clean -purge" on holes_module in its own design | Eddie Hung | 2019-08-07 | 1 | -6/+11 |
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| * | | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor | Clifford Wolf | 2019-08-07 | 1 | -93/+203 |
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| | * | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog... | Jim Lawson | 2019-07-31 | 1 | -93/+203 |
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| * | | | Merge pull request #1241 from YosysHQ/clifford/jsonfix | David Shah | 2019-08-07 | 1 | -13/+37 |
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| | * | | Implement improved JSON attr/param encoding | Clifford Wolf | 2019-08-01 | 1 | -13/+37 |
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| * | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 6 | -3/+40 |
| * | | Merge pull request #1238 from mmicko/vsbuild_fix | Clifford Wolf | 2019-08-02 | 1 | -1/+1 |
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| | * | | Visual Studio build fix | Miodrag Milanovic | 2019-07-31 | 1 | -1/+1 |
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| * / | Fix formatting for msys2 mingw build using GetSize | Miodrag Milanovic | 2019-08-01 | 1 | -6/+6 |
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| * | Merge pull request #1203 from whitequark/write_verilog-zero-width-values | Clifford Wolf | 2019-07-18 | 1 | -1/+2 |
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| | * | write_verilog: dump zero width constants correctly. | whitequark | 2019-07-16 | 1 | -1/+2 |
| * | | Remove old $pmux_safe code from write_verilog | Clifford Wolf | 2019-07-17 | 1 | -5/+4 |
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| * | smt: handle failure of setrlimit syscall | N. Engelhardt | 2019-07-15 | 1 | -1/+5 |
| * | Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark | Clifford Wolf | 2019-07-11 | 1 | -2/+8 |
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| | * | write_verilog: write RTLIL::Sa aka - as Verilog ?. | whitequark | 2019-07-09 | 1 | -2/+8 |
| * | | Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position | Clifford Wolf | 2019-07-09 | 1 | -3/+2 |
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| | * | | write_verilog: fix placement of case attributes. NFC. | whitequark | 2019-07-09 | 1 | -3/+2 |
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| * | | Merge pull request #1170 from YosysHQ/eddie/fix_double_underscore | Eddie Hung | 2019-07-09 | 1 | -4/+6 |
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| | * | Rename __builtin_bswap32 -> bswap32 | Eddie Hung | 2019-07-09 | 1 | -4/+6 |
| * | | verilog_backend: dump attributes on SwitchRule. | whitequark | 2019-07-08 | 1 | -0/+1 |
| * | | verilog_backend: dump attributes on CaseRule, as comments. | whitequark | 2019-07-08 | 1 | -6/+10 |
| * | | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -0/+5 |
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| * | write_xaiger to treat unknown cell connections as keep-s | Eddie Hung | 2019-07-02 | 1 | -6/+14 |
| * | Add generic __builtin_bswap32 function | Eddie Hung | 2019-06-28 | 1 | -0/+15 |
| * | Also fix write_aiger for UB | Eddie Hung | 2019-06-28 | 1 | -26/+26 |
| * | Fix more potential for undefined behaviour due to container invalidation | Eddie Hung | 2019-06-28 | 1 | -6/+10 |
| * | Refactor for one "abc_carry" attribute on module | Eddie Hung | 2019-06-27 | 1 | -42/+40 |
| * | Merge origin/master | Eddie Hung | 2019-06-27 | 2 | -4/+31 |
| * | Improve debugging message for comb loops | Eddie Hung | 2019-06-26 | 1 | -4/+6 |
| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-24 | 1 | -0/+4 |
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| | * | Fix json formatting | Miodrag Milanovic | 2019-06-21 | 1 | -1/+1 |
| | * | Add upto and offset to JSON ports | Miodrag Milanovic | 2019-06-21 | 1 | -0/+4 |
| * | | Carry in/out box ordering now move to end, not swap with end | Eddie Hung | 2019-06-22 | 1 | -26/+34 |
| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-21 | 1 | -0/+4 |
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| | * | Added JSON upto and offset | Clifford Wolf | 2019-06-21 | 1 | -0/+4 |
| | * | Fix gcc invalidation behaviour for write_aiger | Eddie Hung | 2019-06-20 | 1 | -1/+2 |
